Patent
1975-10-30
1977-03-01
Claffy, Kathleen H.
179 15AF, H04J 306
Patent
active
040103250
ABSTRACT:
In a digital multiplexer which employs pulse stuffing and a plurality of signaling bits including evenly spaced framing bits, a framing circuit consists essentially of a pair of flip-flops which store the last values of a winking framing signal or the error signal which may have occurred during the framing time slots. Outputs of the flip-flops are connected to gating circuits. One said gate produces an output signal when an error occurs. This error signal is applied to an error density detector. When an out-of-frame condition occurs, i.e., the receiving circuit is considered not to be synchronized with the transmitting circuit, the error density detector output which is applied to a clock pulse generator causes an extended count to occur for each error occurrence. This offsets the bit stream by one time slot for each error following the out-of-frame condition, and this extended count follows the extended count due to the presence of a signaling bit. A control bit generator operates under the control of the reconstructed clock signal, the clock pulse generator, the sample counter, and the framing circuit. When the out-of-frame condition causes an extended count, the control bit generator does not advance. However, the error is cleared by the end of the first time slot following the second extended count. If the winking framing signal is "in frame", the extra count is inhibited. The framing and/or reframing process is accomplished more readily by means of a preview circuit which consists of an additional flip-flop and two additional gates. The flip-flop stores the last value of the bit following the control bit. If the winking framing signal is out of frame and an error occurs, the counters in the control bit clock generator are shifted such that the bit in the additional flip-flop is now the previous framing bit. Thus, the next framing bit must be the opposite to be correct. The additional gates are used to reset or preset the control bit generator so that a predetermined framing bit will be made available to compare with the incoming framing signal.
REFERENCES:
patent: 3557314 (1971-01-01), Avignon
patent: 3770897 (1973-11-01), Haussmann
patent: 3903371 (1975-09-01), Colton
patent: 3909541 (1975-09-01), Bobilin
Cannon Russell A.
Claffy Kathleen H.
Cool Leonard R.
GTE Automatic Electric Laboratories Incorporated
Heid David W.
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