Multiplex communications – Communication techniques for information carried in plural... – Adaptive
Reexamination Certificate
1999-03-24
2004-07-13
Olms, Douglas (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Adaptive
C370S506000
Reexamination Certificate
active
06763036
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to framing circuits generally and, more particularly, to a programmable circuit for framing a serial bit stream that operates in a received symbol clock domain.
BACKGROUND OF THE INVENTION
Conventional approaches to framing serial bit streams locate a framing symbol in a high-speed serial clock domain. Framing is accomplished by modifying transitions of the received symbol clock in response to detection of the framing symbol. The symbol clock is stretched or compressed as necessary to maintain the framing of symbols to the symbol clock. Programmable selection of the framing symbol may be accomplished using conventional approaches, but is limited to programming the framing symbol in the high speed clock domain.
Conventional approaches require high-speed logic to implement the framing function. The high speed logic requires additional care in design and results in a circuit that requires high power consumption to frame the serial input. Symbol clock duty cycle discontinuities created by such conventional approaches are problematic to synchronous down-stream processing of the received symbols.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.
The objects, features and advantages of the present invention include providing a framing circuit that may (i) have programmable selection of a framing symbol in a received symbol clock domain, (ii) be implemented without high-speed logic and/or (iii) reduce the impact of duty cycle discontinuities on downstream processing.
REFERENCES:
patent: 4203008 (1980-05-01), Cohn-Sfetcu et al.
patent: 4674088 (1987-06-01), Grover
patent: 4748623 (1988-05-01), Fujimoto
patent: 4984249 (1991-01-01), Long
patent: 5003599 (1991-03-01), Landry
patent: 5005191 (1991-04-01), O'Connor et al.
patent: 5010559 (1991-04-01), O'Connor et al.
patent: 5014272 (1991-05-01), Yoshida
patent: 5081654 (1992-01-01), Stephenson
patent: 5161124 (1992-11-01), Love
patent: 5204883 (1993-04-01), Blanc
patent: 5367544 (1994-11-01), Bruekheimer
patent: 5598424 (1997-01-01), Erickson et al.
patent: 5666547 (1997-09-01), James
patent: 5694056 (1997-12-01), Mahoney et al.
patent: 5790607 (1998-08-01), Burke et al.
patent: 5960007 (1999-09-01), Grivna
patent: 5982786 (1999-11-01), Grivna
Edward Grivna, U.S.S.N. 08/976,072, Circuits and Methods for Framing One or More Data Streams, filed Nov. 21, 1997.
Edward Grivna, U.S.S.N. 08/975,644, Circuits and Methods for Framing One or More Data Streams, filed Nov. 21, 1997.
Grivna Edward L.
Maas Michael F.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Olms Douglas
Pizarro Ricardo M.
LandOfFree
Framer method architecture and circuit with programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Framer method architecture and circuit with programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Framer method architecture and circuit with programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3219286