Framed packet bus with improved FPB protocol

Details Framed packet bus with improved FPB protocol Framed packet bus with improved FPB protocol

2005-08-16

2005-08-16

Chin, Wellington (Department: 2664)

Multiplex communications

Communication techniques for information carried in plural...

Transmission bandwidth conservation

C370S442000, C370S437000

Reexamination Certificate

active

06931027

ABSTRACT:
In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.

REFERENCES:
patent: 5243699 (1993-09-01), Nickolls et al.
patent: 5428611 (1995-06-01), Jain et al.
patent: 5822328 (1998-10-01), Derby et al.
patent: 6609167 (2003-08-01), Bastiani et al.
patent: 6629288 (2003-09-01), Bernath et al.

Affiliated with

Also associated with

Rating

Framed packet bus with improved FPB protocol does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Framed packet bus with improved FPB protocol, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Framed packet bus with improved FPB protocol will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3496602