Television – Format conversion – Specified chrominance processing
Reexamination Certificate
1997-10-17
2001-07-10
Lee, Michael (Department: 2614)
Television
Format conversion
Specified chrominance processing
C348S456000
Reexamination Certificate
active
06259481
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame to field converter and, more particularly, to a frame to field converter for use in connection with the decoding of compressed digital video data such as MPEG encoded video data.
BACKGROUND OF THE INVENTION
In many applications, an intelligence bearing signal is encoded, transmitted, and received in the form of plural blocks of data. Depending on the manner in which the blocks were generated, and depending upon their ultimate use, it is frequently necessary to transpose the blocks of data from the order in which they are received to a different order conforming with their intended use.
For example, in a television system which processes digital video pictures, each digital video picture is typically divided into a rectangular array having plural lines of video data, where each line of video data is comprised of a plurality of pixel values. The video data for what is known as an interlaced video sequence of pictures is characterized by a frame rate which is typically 30 Hz, and each frame is composed of two interlaced fields. The first field consists of the odd numbered lines of the frame (i.e., the lines numbered
1
,
3
,
5
, . . . ), and the second field consists of the even numbered lines of the frame (i.e., the lines numbered
2
,
4
,
6
, . . . ).
This interlaced video sequence may be encoded, typically by an MPEG-2 video encoder. The MPEG-2 video encoder may arbitrarily choose to encode the video data of a picture as either a frame or as separate fields. If the MPEG-2 video encoder chooses frame encoding, the video picture data is effectively encoded and transmitted in frame order (i.e., lines
1
,
2
,
3
,
4
, . . . are transmitted, in order, for that picture). If the MPEG-2 video encoder chooses field encoding, the video picture data is effectively encoded and transmitted in field order (i.e., lines
1
,
3
,
5
, . . . followed by lines
2
,
4
,
6
, . . . are transmitted, in order, for that picture). The MPEG-2 video encoder may change its encoding decision from picture to picture.
An MPEG-2 video decoder which receives this encoded video picture data must decode this interlaced video sequence and produce decoded pixel values in field order so that the pixel values can be displayed by a video display device which displays video data as interlaced fields. This decoding must be done whether the incoming encoded video picture data is in field order or frame order. Thus, when the incoming encoded video picture data is in frame order, the frame ordered decoded data must be converted to field order before it is sent to the interlaced display device. As discussed immediately below, the conversion of frame ordered video data to field ordered video data typically requires some amount of memory because lines of pixels must be output by a frame to field convertor in a different order than the order in which they were received and decoded.
That is, for the case of I and P type pictures, MPEG video decoding requires that these types of pictures be decoded and stored in memory so that the pixel data comprising these pictures may be used in the processing of other pictures. These I and P type pictures do not exit the decoder until they have been completely decoded and stored in memory. However, in the case of B type pictures, MPEG video decoding does not require storage because B type picture data is not used in the processing of other pictures. B type pictures can in principle be decoded and sent to the display device without storing them in memory.
When I and P type pictures are decoded in frame order and are stored in memory as required, they can easily be read out of memory in field order. No additional memory needs to be added to the system in order to achieve this conversion. B type pictures encoded in frame order, however, require some amount of memory to be added to the system so that they can be converted to field order.
A simple way of performing this conversion is to use two additional frame-size memories. As frame or field order data for picture n is stored in the first of these memories, the data for picture n−1 previously stored in the second of these memories is read out in field order. Then, when frame or field order data for picture n+1 is received, this data is stored in the second of these memories as the data for picture n previously stored in the first of these memories is read out in field order. This type of convertor requires a memory size of two frames, which adds to the expense of the converter.
The present invention is directed to a frame to field converter which employs a memory having a reduced size.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a frame to field converter comprises a memory and an address generator. The frame to field converter converts input frames of video data to output fields of video data. The input frames include input lines of video data, and the output fields include output lines of video data. The memory is limited in size to substantially one field. The address generator is arranged to address the memory so that, as each output line of video data is written out of the memory, it is replaced by an input line of video data.
In accordance with another aspect of the present invention, a frame to field converter comprises a converter memory and an address generator. The address generator is arranged to repetitively generate a set of different address sequences and to sequentially apply the addresses of successive ones of the generated address sequences to the converter memory so that a first group of lines is written into the converter memory in frame order, so that the first group of lines is read out of the converter memory in field order and a second group of lines is written into the converter memory in frame order, and so that as each line of the first group of lines is read out of the converter memory, it is replaced by a line of the second group of lines before a next line of the first group of lines is read out of the converter memory.
In accordance with yet another aspect of the present invention, a frame to field converter comprises a converter memory and an address generator. The address generator is arranged to repetitively generate a set of address sequences and to sequentially apply the addresses of successive ones of the generated address sequences to the converter memory. A first sequence of addresses has a first portion of addresses and a second portion of addresses. No address is repeated in the first portion of addresses. The addresses of the second portion of addresses and the addresses of the other address sequences in the set of address sequences are determined from the first portion of addresses based upon the following delay pattern: L/2, L−1, (L/2)−1, L−2, (L/2)−2, L−3, (L/2)−3, . . . , 1, L/2, where L is the number of lines in a frame and is constrained to be even.
REFERENCES:
patent: 5170251 (1992-12-01), Levy
patent: 5231490 (1993-07-01), Park
patent: 5754247 (1998-05-01), Tauchi
patent: 5861879 (1999-01-01), Shimizu et al.
patent: 5896178 (1999-04-01), Inoue
Bretl Wayne E.
Fimoff Mark
Lee Michael
Zenith Electronics Corporation
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