Frame-synchronous reproducing circuit

Details Frame-synchronous reproducing circuit Frame-synchronous reproducing circuit

1995-07-07

1998-02-17

Safourek, Benedict V.

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370514, 375366, 375368, H04L 700

Patent

active

057198730

ABSTRACT:
A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

REFERENCES:
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patent: 4763339 (1988-08-01), Sutphin et al.
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patent: 5297185 (1994-03-01), Best et al.
patent: 5299236 (1994-03-01), Pandula
patent: 5339337 (1994-08-01), Levine
patent: 5428647 (1995-06-01), Rasky et al.
patent: 5509036 (1996-04-01), Nakata

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