Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-08-19
2002-03-19
Marcelo, Melvin (Department: 2733)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S509000, C370S514000
Reexamination Certificate
active
06359908
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a frame synchronous circuit in terms of time-division multiplex signal. More to particularly this invention relates to a frame synchronous circuit contributing to SDH signal.
Description of the Related Art
In ITU-T (International Telecommunication Unions International Telecommunication Standardization Department), an interface within network is standardized under the name of SDH-NNI (Synchronous Digital Hierarchy Network Node Interface) by way of purpose of an improvement for operation of a network. Under the state of things, STM-N (Synchronous Transport Module-N ; N=1, 2, 3, . . . ) signal is established by way of signal which N pieces of STM-
1
frame construction is subjected to byte multiplexing.
Under normal conditions, in order to perform a frame synchronization of the STM-N signal, the action of frame synchronization is performed while detecting A
1
, A
2
byte-pattern for frame synchronization existing within SOH (Section Overhead) of the STM-N signal.
In the Japanese Patent Application Laid-Open No. HEI 8-163116, an example in which quantity of hardware is intended to stay as few as possible is described by way of the conventional frame synchronous circuit.
FIG. 1
is a view showing configuration of a frame synchronous circuit described in the official gazette of the above Application No. HEI 8-163116. In
FIG. 1
, a reference numeral
50
denotes a shift register for converting a serial data DATA of input into parallel data, reference numerals
51
-
58
denote D-type flip-flop (D-F/F) constituting the shift register, reference numerals
71
-
78
denote D-F/F for taking data with the timing of clock CLK
1
from the serial-parallel converter, reference numerals
81
, and
82
denote AND gate for detecting respective A
1
byte-pattern and A
2
byte-pattern with output of respective stages of the shift register
50
as the input, a reference numeral
83
denotes a selector for selecting detection signal of the AND gates
81
and
82
, and reference numerals
61
, and
62
denote an inverter and a D-F/F for supplying the fan out of the selector
83
to the D-F/Fs
71
to
78
with the timing which is shifted by half cycle in relation to input clock CLK.
In this frame synchronous circuit, which causes verification to be performed whether or not the pattern of data of the shift register
50
is A
1
-byte. If the state of selector
83
is set so as to select the output of AND gate
81
, when the data inputted to the shift register
50
comes to be A
1
-byte, the logic of output of the AND gate
81
due to the data pattern becomes “1”, thus this is outputted from the selector
83
. Under the state, the D-F/F
62
outputs the logic “1” to generate the clock CLK
1
with the timing of the clock CLK from the inverter
61
. The D-F/Fs
71
to
78
take in data of the shift register
50
with leading edge of the clock CLK
1
in parallel. Subsequently, the data is read with this timing, thus the signal which a phase of byte unit corresponds therewith being outputted.
In the above described conventional frame synchronous circuit, the synchronous operation from detection of A
1
-byte until generation of the clock CLK should be terminated within one time slot of input clock CLK. If the speed of input data is slow, such circuit system is in use sufficiently. However, in the case of high speed data such as STM-
64
, even if circuit is arranged by bipolar device of the highest speed, the time to require from detection of A
1
-byte until generation of the clock CLK
1
takes more than 1 time slot, thereby it becomes difficult to perform timing control of generation of the clock CLK
1
, with the result that there is the problem that the frame synchronization does not materialize.
SUMMARY OF THE INVENTION
In view of the foregoing it is an object of the present invention to provide a frame synchronous circuit which has a simple configuration and which is capable of operating certainly in relation to the high speed SDH signal.
In one arrangement to be described below by way of example in illustration of the invention, a frame synchronous circuit includes a first and a second shift registers for inputting an SDH (Synchronous Digital Hierarchy) signal alternately in every 1 bit, a first and a second A
1
-byte detecting logic device for detecting an A
1
-byte from respective inputs which are inputted thereto by way of two sets of outputs for 1 byte which are shifted with each other by 1 bit, from among respective outputs of the first and the second shift registers, a latched-circuit for latching to output data with 1 byte as a unit from output of the first and the second shift registers while synchronizing with detected output of the first A
1
-byte detecting logic device, and a switching circuit for switching data input order of the SDH signal inputted to the first and the second shift registers by virtue of detected output of the second A
1
-byte detecting logic device.
In one particular arrangement to be described in illustration of the present invention, by way of example, wherein the switching circuit comprises 1-bit shift circuit for performing 1-bit shift of the SDH signal of detected output of the second A
1
-byte detecting logic device.
In one yet particular arrangement to be described in illustration of the present invention, by way of example, wherein there is provided a counter circuit for controlling latching of the latched-circuit by 1-byte cycle of the SDH signal with detected output of the first A
1
-byte detecting logic device as set input of determined value.
In another arrangement to be described below by way of example in illustration of the present invention, a frame synchronous circuit includes a delay circuit which is capable of outputting data slowed by 1-bit in relation to input data by selection signal, a frequency division circuit for frequency dividing input clock by ½, a first and a second shift register circuits for shifting data successively by using frequency division clock signal of the frequency dividing circuit while inputting output signal of the delay circuit, a counter circuit for performing counter operation by inputting frequency division clock signal of the frequency dividing circuit and the counter circuit which is capable of setting the counter to a determined value by virtue of set signal, an A
1
-byte detecting circuit to which data of determined bit number shifted from output of the first and the second shift registers by 1-bit each other is inputted, detecting the A
1
-byte of the SDH (Synchronous Digital Hierarchy) frame, and outputting respective detected outputs by way of selection signal of the delay circuit and set signal of the counter circuit, and a first and a second latched-circuit to which the output of the first and the second shift registers is inputted to perform latching by the output signal of the counter circuit.
In one particular arrangement to be described below by way of example in illustration of the invention, wherein the first shift register comprises a first flip-flop for latching an input data at trailing edge of a frequency division clock signal and for maintaining signal from the time point of latching until leading edge of next frequency division clock signal, and a second to a fourth flip-flops for latching an input data at leading edge of a frequency division clock signal and for maintaining data from the time point of latching until next leading edge of the frequency division clock signal, and wherein the second shift register comprises a first to a fifth flip-flops for latching input data at leading edge of the frequency division clock signal and for maintaining data from the time point of latching until next leading edge of the frequency division clock signal.
In one yet particular arrangement to be described below by way of example in illustration of the present invention, wherein the A
1
-byte detecting circuit comprises a first logic gate circuit for outputting the selection signal with both outputs of the first to fourth flip-flops of the
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