Frame synchronizing system in a receiver in a time-division mult

Details Frame synchronizing system in a receiver in a time-division mult Frame synchronizing system in a receiver in a time-division mult

1985-06-21

1987-01-20

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370101, H04J 326

Patent

active

046384782

ABSTRACT:
In a receiver receiving a time-division multiplex signal of a plurality of channels with each channel signal having a start signal part, an address signal, an error detecting code signal part, an information signal part, and a blank interval arranged in this order, a channel detecting circuit for detecting the channel signal assigned to the receiver is provided with a blank interval detecting circuit in addition to an address detecting circuit, in order to avoid an erroneous detection of the address detection circuit at a start condition of the receiver. Application of the multiplex signal to the address detecting circuit is prevented until the blank interval detection circuit initially detects one blank interval of the multiplex signal. At a start condition of the receiver, application of the multiplex signal to the address detecting circuit starts not at an intermediate time position in one channel signal but at the start signal part of a subsequent channel signal. The channel detecting circuit is further provided with a circuit for detecting an incorrect synchronization condition by observing the error detecting code signal part. The incorrect synchronization detecting circuit, when detecting the incorrectly synchronized condition, resets the blank interval detecting circuit into an initial condition, so that the acquisition operation of the frame synchronization is carried out. Thus, the frame synchronization is established even if noise invades the multiplex signal as transmitted.

REFERENCES:
patent: 4471481 (1984-09-01), Shaw et al.
patent: 4516239 (1985-05-01), Maxemchuk

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