Frame synchronizing circuit for frame synchronization of digital

Television – Synchronization – Sync separation

Patent

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Details

348526, 3701054, 375368, H04N 508

Patent

active

054424054

ABSTRACT:
A frame synchronizing apparatus is disclosed which includes a serial-parallel converter for converting input serial data into parallel data of a plurality of channels; a plurality of intra-channel synchronization detecting circuits each for detecting a synchronization pattern and a pseudo-synchronization pattern in one channel, and generating a channel synchronization detect signal and a pseudo-synchronization detect signal in one channel; a plurality of bit-shift error pattern detecting circuits each for detecting a bit-shift error pattern in one channel, and generating a bit-shift error pattern signal in one channel; a synchronization/bit-shift error detecting circuit for detecting a synchronization between channels and specifying the amount of erroneously shifted bits, and generating a frame synchronization detect signal and bit-shift error detect signals; and a bit-shift signal generating circuit for calculating the number of erroneously shifted bits in the serial-parallel converter based on the bit-shift error detect signals and the bit-shift error pattern signals, and generating a bit-shift signal to be supplied to the serial-parallel converter, whereby bits of the calculated number are shifted.

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