Frame synchronizer having a write-inhibit circuit

Details Frame synchronizer having a write-inhibit circuit Frame synchronizer having a write-inhibit circuit

1979-05-16

1980-10-28

Martin, John C.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358181, 358 19, H04N 504, H04N 522, H04N 946

Patent

active

042310636

ABSTRACT:
A frame synchronizer for a television receiver in which the incoming television signal is digitized and stored in a memory, includes a circuit for generating a write-inhibit control signal for inhibiting the write-in of a digitized second television signal into the memory between the switchover from a first television signal to the second television signal and the beginning of a complete frame of the second television signal.

REFERENCES:
patent: 3909839 (1975-09-01), Inaba et al.
patent: 4007486 (1977-02-01), Inaba et al.
patent: 4018990 (1977-04-01), Long et al.
Matley, "A Digital Framestore Synchronizer", SMPTE Journal, vol. 85, No. 6, pp. 385-388, Jun. 1976.
Kano et al., "Television Frame Synchronizer", SMPTE Journal, vol. 84, No. 3, pp. 129-134, Mar. 1975.

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