Frame synchronization of multiply redundant computers

Details Frame synchronization of multiply redundant computers Frame synchronization of multiply redundant computers

1985-12-13

1988-03-22

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

047333537

ABSTRACT:
A frame synchronization method and apparatus wherein each computer system of a multiply redundant processing system periodically executes a frame synchronization procedure in which it sequentially assumes a plurality of different operating states during which it pauses in the execution of a task it was performing and readies itself for synchronization, determines which other computer systems are ready for synchronization, synchronizes itself with one or more of the systems, and then determines which of the other systems has also synchronized itself. At a predetermined frame interval, the procedure is repeated and the computer systems resynchronize themselves with one another. The invention is impervious to stuck-at type faults, and may be embodied either totally or partially in software within each computer system, or in a separate hardware device.

REFERENCES:
patent: 3803568 (1974-04-01), Higashide
patent: 3896418 (1975-07-01), Brown
patent: 3961270 (1976-06-01), Ullmann et al.
patent: 4330826 (1982-05-01), Whiteside et al.
patent: 4404675 (1983-09-01), Karchevski
patent: 4408327 (1983-10-01), Wahl et al.
patent: 4412342 (1983-10-01), Khan et al.
Smith, T. B.; "Fault Tolerant Clocking System", Digest of Papers, 11th Int'l Symposium, Charles Stark Draper Laboratory, Inc., Cambridge, Mass., pp. 262-264, Jun. 1981.
IEEE Transactions on Computers, vol. C-27, No. 6, Jun. 1978, pp. 531-539.

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