Frame synchronization detection system

Details Frame synchronization detection system Frame synchronization detection system

1987-01-07

1989-01-03

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

370105, H04L 700

Patent

active

047962828

ABSTRACT:
In a frame synchronization system for synchronizing a frame consisting of N sub-frames each consisting of M bits, a transmitting side includes a circuit for generating an N-bit cyclic code from a generating polynomial and sequentially and respectively inserting bits of the cyclic code in bit positions of the sub-frames, and a receiving side includes a divider for dividing a code polynomial having N-bit values of the data trains as coefficients by the generating polynomial to output the remainder, and a frame synchronization detector for sending a frame synchronization clock signal to the N-bit data train producing circuit when the remainder from the divider is zero.

REFERENCES:
patent: 3952162 (1976-04-01), Texier et al.
patent: 4316284 (1982-02-01), Howson
patent: 4594728 (1986-06-01), Niquel et al.

Affiliated with

Also associated with

Rating

Frame synchronization detection system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Frame synchronization detection system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frame synchronization detection system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2173812