Frame synchronization dependent type bit synchronization extract

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

375120, 375118, 3701051, H04L 700

Patent

active

052590046

ABSTRACT:
A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data. To make the timing extraction jitter small and make the bit timing stable, it comprises a counter preset mode synchronization unit, a digital phase-lock loop mode synchronization unit, frame synchronization detection unit, and an inhibiting unit for inhibiting the operation of the counter preset mode synchronization unit, and the bit synchronization is effected by only the digital phase locked loop mode synchronization unit after the frame synchronization is detected by the frame synchronization detection unit.

REFERENCES:
patent: 3671776 (1972-06-01), Houston
patent: 4694259 (1987-09-01), Carickhoff et al.
patent: 4775989 (1988-10-01), Takatori et al.
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 4933959 (1990-06-01), Knechtel
M. Fukuda et al., An Echo Canceller LSI for ISDN Subscriber Loop Transmission, Jun. 7-10, 1987, pp. 596-600, Seattle, US.

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