Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-10-13
2004-05-18
Olms, Douglas (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S503000, C370S505000, C370S509000, C370S510000, C370S470000
Reexamination Certificate
active
06738393
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a frame synchronization circuit suitable to transmitting data sequence which have a frame composition in an environment where a code error, especially a data loss or data insertion in units of cells or packets, is likely to be generated.
BACKGROUND OF THE INVENTION
Conventionally, in a data transmission system in which information data to be transmitted is transmitted in frame units, a method for adding a unique word such as M sequence to each frame as a frame synchronization code has been widely used on its transmitting side. The position to which the unique word is added is not particularly defined in this method, but in general, the unique word is set to the head of a frame to simplify the composition, as shown in FIG.
1
A. The unique word in the received data sequence is detected on the reception side, so that the frame position is identified to detect each frame and the transmitted information data is reproduced from each frame detected.
However, there is a disadvantage that an out of detection can occur. This is where detection of the unique word is prevented where the code error is likely to be generated. As such, there is proposed a technique in which the resistance to the burst code error is improved by positioning unique words scatteredly within a frame.
An example of a frame composition according to this technique is shown in
FIGS. 1B and 1C
. These figures show arrangements of identical unique words.
FIG. 1C
displays information data for every block of predetermined length (M+1 bits) and
FIG. 1B
expands the information data for every one bit. In
FIG. 1C
, unique words are constituted of the most significant bit (bits Sl to SN) of each block, and the signal shown in
FIG. 1B
can be obtained by expanding the unique words to serial data from high order bit sequentially.
In the example shown in
FIG. 1B
, the unique words Sj (j=1 to N) are assigned one bit to each uniform interval (M bits) in a transmission information data sequence. However, the intervals assigned may be nonuniform and also plural bits may be assigned. Incidentally, M and N are natural numbers.
Most of the unique words would survive even if a burst code error is generated in a transmission channel by positioning unique words scatteredly in this way, so that a failure to detect any of the unique words is avoided by permitting variations in of the number of constant bits at the time of detection, allowing detection of the unique words with high probability. Incidentally, If the variation in the number of bits is too large compared with the unique word length, false detection may occur, where part of the information data is detected by mistake as a unique word, so that the size of the allowable variation in bits and the unique word length must be set such that the probability of a false detection can be minimized.
Moreover, if a frame length is variable, to achieve higher frame synchronization property, frame length information can also be used in addition to the unique word as a frame synchronization code, as shown in FIG.
1
D. An appearance position of the following frame synchronization code can be known on the reception side by using the frame length information, so that the probability of an out of detection or false detection of the frame synchronization code can be reduced compared to the case in which only the unique word is used.
Next, there are described the composition and operation of a conventional frame synchronization circuit. Incidentally, as a method for adding unique words to a frame, a head arrangement or scattered positioning described above can be considered, and there is no influence in the following explanation even if either is adopted.
A. In the Case of a Fixed Length Frame
FIG. 2
shows a composition of a conventional frame synchronization circuit (Example 1). The frame synchronization circuit shown in
FIG. 2
may be utilized in a transmission system of a fixed length frame. As shown in
FIG. 2
, a received data sequence input from an input terminal
11
is sent to a unique word detector
12
. In the unique word detector
12
, an input buffer
15
buffers the received data sequence sent from the input terminal
11
, cuts out data equivalent to the unique word length at every predetermined timing to supply the data to a comparator
16
, and then shifts a cut out position of the data by one bit at every same timing.
The comparator
16
compares the data supplied from the input buffer
15
and the unique word sent from a unique word generator
17
, and generates a “1” when the data is in accordance with the unique word or “0” when there is a variation. The single generated by comparator
16
is sent to a synchronization judgment circuit
13
as a comparison result. In order to prevent the out of detection based on code error occurring when comparison operation is performed in the comparator
16
, the disagreement of the number of constant bits may be set so as to provide “agreement”.
Next, the operation of the synchronization judgment circuit
13
will be described.
FIG. 3
is a state transition chart of the synchronization judgment circuit
13
. The synchronization judgment circuit
13
is, at first, in an out of synchronization state S
1
in which frame synchronization is not established at all. The synchronization judgment circuit
13
in the out of synchronization state S
1
transfers its own state to a backward 1 state S
2
as “detection”, when “1” is supplied from the comparator
16
, and holds its own state in the out of synchronization state S
1
as “out of detection”, when “0” is supplied.
The synchronization judgment circuit
13
transferred to the backward 1 state S
1
skips the received data sequence by the fixed frame length to wait for the output of the comparator
16
. When the comparison result from the comparator
16
is “1”, the synchronization judgment circuit
13
transfers its own state to a next backward 2 state S
3
as “detection”, and when it is “0”, returns back to the out of synchronization state S
1
as “out of detection”. The processing similar to that described above is also performed in states after the backward 2, and the state of the synchronization judgment circuit
13
returns immediately back to the out of synchronization state S
1
in the case of out of detection, and advances toward a synchronization establishment state S
5
when “detection” continues for total of N+1 times.
Here, the states from the backward 1 to the backward N are set to reduce occurrence frequency of false synchronization, and generally, such setting is called “backward protection”. When the backward protection is not set up, if the part which agrees with a unique word accidentally exists somewhere in the part other than a unique word in the received data sequence, a false detection which detects the unique word by mistake may occur, resulting in frequent false synchronization. However, the synchronization judgment circuit
13
illustrated in the present invention is provided with backward protection and also repeats agreement judgment for N+1 times to reduce the occurrence frequency of the false synchronization due to false detection.
Moreover, the synchronization judgment circuit
13
, even when in the synchronization establishment state S
5
, skips the received data sequence only by the fixed frame length to wait for an output from the comparator
16
. When “1” is supplied from the comparator
16
, the synchronization judgment circuit
13
retains its own state in the synchronization establishment state S
5
as “detection”, and when “0” is supplied, transfers its own state to a forward 1 state S
6
as “out of detection”. The processes in the states from the forward 1 to a forward M are opposite those in the states from the backward 1 to the backward N described above, and in the case of “detection”, the process returns immediately to the synchronization establishment state S
5
, and when “out of detection” continues for total of M+1 times, the process returns back to the out of s
Hotani Sanae
Miki Toshio
Nguyen Van
NTT Mobile Communications
Olms Douglas
LandOfFree
Frame synchronization circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frame synchronization circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frame synchronization circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3194873