Pulse or digital communications – Synchronizers – Synchronization failure prevention
Reexamination Certificate
1999-08-25
2003-07-01
Phu, Phuong (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronization failure prevention
C375S368000, C370S509000
Reexamination Certificate
active
06587527
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates to a frame synchronism processing apparatus and a frame synchronism processing method suitable for use in a case wherein data transmission is carried out using a predetermined frame.
2) Description of the Related Art
A frame synchronism processing apparatus is arranged to detect information for synchronization acquisition (frame synchronism establishment) in a transmission signal (transmission frame) so that frame synchronism is established. For example, if a frame to be transmitted is a DS
3
(Digital Signal-Level
3
) signal, a frame synchronism processing apparatus
1
a
is arranged to include a DS
3
subframe synchronism detecting unit (DS
3
subframe Sync unit)
2
a
, a DS
3
multiframe synchronism detecting unit (DS
3
multiframe Sync unit)
3
a
, an OR circuit
6
b
, and a data inhibit
ibble switch unit (Data Inhibit+Nibble SW)
6
a
, as shown in FIG.
12
.
It is to be noted that, as shown in
FIG. 9
, a frame format of a DS
3
signal is formed as a DS
3
multiframe which includes seven DS
3
subframes each including a plurality of sets of an overhead part and a payload part. The overhead part (1 bit) in the DS
3
subframes has information unique in the DS
3
multiframe such as “F
1
”, “F
2
”, “F
3
”, “F
4
”, “M
1
”, “M
2
”, “M
3
”, “X
1
”, “X
2
” and so forth stored therein as seen from FIG.
9
.
Here, each of “F
1
”, “F
2
”, “F
3
”, and “F
4
” is a bit representative of a synchronizing pattern of a DS
3
subframe, and fixed patterns of “1”, “0”, “0” and “1” are allocated to them. Meanwhile, each of “M
1
”, “M
2
”, and “M
3
” is a bit representative of a synchronizing pattern of a DS
3
multiframe, and fixed values of “0”, “1” and “0” are allocated to them. It is to be noted that various data are mapped in the payload part (84 bits).
Referring back to
FIG. 12
, the DS
3
subframe synchronism detecting unit
2
a
detects synchronism of received DS
3
subframes. In particular, the DS
3
subframe synchronism detecting unit
2
a
detects bits (“F
1
”, “F
2
”, “F
3
”, “F
4
”) in the DS
3
subframes and discriminates whether or not they coincide with the synchronizing pattern (“1”, “0”, “0”, “1”). If the DS
3
subframe synchronism detecting unit
2
a
detects coincidence with the synchronizing pattern, then it outputs a signal indicating this to the DS
3
multiframe synchronism detecting unit
3
a.
If the synchronism of the DS
3
subframes is detected by the DS
3
subframe synchronism detecting unit
2
a
, then the DS
3
multiframe synchronism detecting unit
3
a
detects predetermined bits (“M
1
”, “M
2
”, “M
3
”) from a plurality of DS
3
subframes and discriminates whether or not the detected bits coincide with the synchronizing pattern (“0”, “1”, “0”).
The data inhibit
ibble switch unit
6
a
inhibits outputting of data while it receives, from any one of the DS
3
subframe synchronism detecting unit
2
a
and the DS
3
multiframe synchronism detecting unit
3
a
through the OR circuit
6
b
, information (out of frame information) that synchronism cannot be detected. However, while the data inhibit
ibble switch unit
6
a
receives, from both the DS
3
subframe synchronism detecting unit
2
a
and the DS
3
multiframe synchronism detecting unit
3
a
, information that synchronism is detected (synchronous state), it extracts the payload parts except the overhead parts from the received DS
3
multiframe and outputs the payload parts.
Since the frame synchronism processing apparatus
1
a
detects the particular bits (“F
1
”=“1”, “F
2
”=“0”, “F
3
”=“0”, “F
4
”=“1”) of DS
3
subframes of a received DS
3
multiframe to detect the synchronism of the DS
3
subframes and then detects the particular bits “M
1
”=“0”, “M
2
”=“1”, “M
3
”=“0”) in the DS
3
multiframe in this manner, the frame synchronism processing apparatus
1
a
can establish the synchronism of the DS
3
frames.
FIG. 10
illustrates a method of mapping an ATM cell in a PLCP (Physical Layer Convergence Protocol) frame. As shown in
FIG. 10
, an ATM cell can be mapped in the payload part in a PLCP frame, and the PLCP frame can be stored into a payload part (84 bits) of a DS
3
frame.
Where a PLCP frame is mapped in a payload part (84 bits) of such a DS
3
frame as described above, for example, as shown in
FIG. 13
, the frame synchronism processing apparatus
1
a
further includes a PLCP frame synchronism detecting unit
4
a
, which in turn includes a detecting unit
4
-
1
a
, a discriminating unit
4
-
2
a
, a POI (Path Overhead Indicator) detecting unit
4
-
3
a
, a POI check unit
4
-
4
a
, a POL (Path Overhead Label)discriminating unit
4
-
5
a
, a frame pattern check unit
4
-
6
a
, and a frame counter (FCTR)
4
-
11
a.
It is to be noted that, for example, as shown in
FIG. 11
, also a frame format of a PLCP signal includes an overhead part
16
and a payload part
17
. It is to be noted that reference numeral
18
denotes a trailer (stuff bits) for bit number adjustment.
Here, the overhead part
16
has framing octets (“A
1
”, “A
2
”), a POI and a POH (Path Overhead) stored therein. “A
1
” and “A
2
” are bits representative of a synchronizing pattern of a PLCP frame and have fixed values of “A
1
”=“F
6
” (hex), “A
2
”=“28” (hex) stored therein, respectively. Further, POI is information indicating that it is followed by a POH.
Referring back to
FIG. 13
, the detecting unit
4
-
1
a
detects “A
1
” and “A
2
” from the PLCP frame described above. The discriminating unit
4
-
2
a
determines whether or not “A
1
”, “A
2
” are equal to “F
6
”, “28”, respectively.
The POI detecting unit
4
-
3
a
detects the POI described above from a PLCP frame. The POI check unit
4
-
4
a
performs a parity check. The POL discriminating unit
4
-
5
a
determines what numbered set (slot) the set is in the entire frame. The frame pattern check unit
4
-
6
a
determines whether or not information received from the discriminating unit
4
-
2
a
, POI check unit
4
-
4
a
and POL discriminating unit
4
-
5
a
satisfies a desired requirement. The frame counter
4
-
11
a
outputs an address of a memory (not shown) into which data outputted from a byte switch
7
a
is to be stored after synchronism is established.
The frame synchronism processing apparatus
1
a
which includes the PLCP frame synchronism detecting unit
4
a
having such a construction as described above detects a synchronizing pattern based on the particular bits (“A
1
”=“F
6
”, “A
2
”=“28”) in a PLCP frame to establish the synchronism of the PLCP frame.
As described above, the frame synchronism processing apparatus
1
a
detects the F bits (“F
1
”, “F
2
”, “F
3
”, “F
4
”) of the DS
3
frame format from received data and detects the M bits (“M
1
”, “M
2
”, “M
3
”) of the DS
3
multiframe after synchronism of DS
3
subframes is detected.
The received data can contain an alarm signal (ALL “0”) such as an AIS (Alarm Indication Signal) if a failure or the like occurs in the connection.
The F bits (“F
1
”, “F
2
”, “F
3
”, “F
4
”) which are a synchronizing pattern of DS
3
subframes are disposed in a distributed condition as seen in
FIG. 9
, and since this synchronizing pattern is a synchronizing pattern of 4 bits, a data train same as the F bits possibly appears in received data as a result of influence of propagation of an AIS.
In this instance, although the pattern in the signal does not correspond to the original DS
3
subframe synchronizing pattern, there is the possibility that the pattern is erroneously detected as the normal synchronizing pattern and a false synchronizing state is brought about.
In this case, the synchronism of the DS
3
multiframe depends upon the synchronism of the DS
3
subframes while the synchronism of the DS
3
subframes does not depend upon the synchronism of the DS
3
multi frame, if the synchronism of DS
3
subframes is erroneously detected in the frame synchronous processing apparatus
1
a
due to a generation of AIS or the like with the result that a false synchronous state is brought
Koyanagi Toshinori
Tani Shigeo
Fujitsu Limited
Katten Muchin Zavis & Rosenman
Phu Phuong
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