Frame resynchronization circuit for digital receiver

Details Frame resynchronization circuit for digital receiver Frame resynchronization circuit for digital receiver

1980-09-11

1982-02-16

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

371 47, 375116, 375108, H04J 306, H04K 704

Patent

active

043162843

ABSTRACT:
Framing of a digital receiver to synchronize with a true framing pattern is realized by employing an autonomous clock to generate framing pattern bits and other timing signal, and by employing a cyclical-redundancy-check (CRC) to eliminate the possibility of framing on false framing patterns. To this end, a frame synchronization circuit detects all possible framing candidate bit positions in a received time division signal and generates a frame resynchronization pulse corresponding to the framing candidate bit positions thereby causing the autonomous clock to synchronize to the associated framing pattern. If the framing pattern on which the clock is synchronized is a false one a loss of CRC signal is generated which initiates synchronizing on the next detected framing pattern. This process is iterated until no loss of CRC signal is generated thereby indicating synchronization on the true framing pattern.

REFERENCES:
patent: 4016368 (1977-04-01), Apple, Jr.
patent: 4032885 (1977-06-01), Roth
patent: 4125745 (1978-11-01), Steidl
patent: 4142070 (1979-02-01), Landauer
patent: 4154984 (1979-05-01), Murasov
patent: 4229792 (1980-10-01), Jensen et al.
"DS-1 Extended Framing Format", USITA Meeting, AT&T Basking Ridge, N.J., Apr. 16, 1980, pp.1-7.

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