Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2005-11-29
2005-11-29
Eisen, Alexander (Department: 2677)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S204000, C345S211000
Reexamination Certificate
active
06970163
ABSTRACT:
A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.
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European Search Report regarding Application No. EP 02 25 1633 dated Sep. 13, 2004.
Brownlow Michael James
Cairns Graham Andrew
Eisen Alexander
Nguyen Kimnhung
Renner , Otto, Boisselle & Sklar, LLP
Sharp Kabushiki Kaisha
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