Frame phase synchronization apparatus and method, and a phase sy

Details Frame phase synchronization apparatus and method, and a phase sy Frame phase synchronization apparatus and method, and a phase sy

1993-12-02

1995-09-19

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701001, 3701051, 370112, H04J 312

Patent

active

054523052

ABSTRACT:
A first frame counter generates a position signal for an input subframe address which is synchronized with an input clock signal based on an input frame phase signal. The first frame counter also generates a write address enabling signal. A subframe type detector generates a write/read control signal based on an input frame signal. Depending upon the position signal for the input subframe address, the write address enabling signal and the write/read control signal, a first subframe phase synchronization device and a second to nth subframe phase synchronization device control a buffer corresponding to 1/m of a frame data amount by a write address, where m (n>=m) is a multiplexing number. The first subframe phase synchronization device and the second to mth subframe phase synchronization device writes data corresponding to a first to mth input subframe signal based on the input frame signal into a buffer respectively. An input relative phase is synchronized with a standard relative phase. The synchronized signal is output as a synchronized frame signal.

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R. W. Hamlin & B. Parruck "A Sonet/SDH Overhead Terminator for STS-3, STS3C and STM-1" IEEE 1992 Custom Integrated Circuits Conference.

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