Frame phase aligning system using a buffer memory with a reduced

Details Frame phase aligning system using a buffer memory with a reduced Frame phase aligning system using a buffer memory with a reduced

1990-09-14

1992-05-12

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701051, H04J 306

Patent

active

051133954

ABSTRACT:
In a frame aligner for frame aligning an input time-division multiplexed (TDM) signal to an output frame synchronous signal, an input frame signal of the TDM signal is separated into a transport overhead carrying an input frame synchronous signal and a message pointer and a subframe carrying data signal. A fresh overhead having a fresh pointer is made corresponding to a phase difference between said input and said output frame synchronous signals and said subframe is sequentially written into and read from a buffer memory. The fresh overhead and the subframe read are multiplexed to form an output TDM frame signal which is synchronized with the output frame synchronous signal. The buffer memory is permitted to have a reduced memory capacity storable a number of channel signals equal to that of time slots carrying the overhead. When the input frame signal is asynchronous with an output clock signal, the input frame signal is converted to a converted frame signal which is synchronized with the output clock signal before the frame alignment is performed.

REFERENCES:
patent: 4606023 (1986-08-01), Dragoo
patent: 4649539 (1987-03-01), Krinock
patent: 4667324 (1987-05-01), Graves
patent: 4819226 (1989-04-01), Beckner et al.
patent: 4833673 (1989-05-01), Chao et al.
patent: 4967410 (1990-10-01), Takase et al.

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