Frame memory control system

Details Frame memory control system Frame memory control system

1989-06-06

1990-09-11

Britton, Howard W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358160, H04N 701

Patent

active

049567080

ABSTRACT:
A frame memory control system includes independent row address counters for generating first and second row addresses, and selectors for selecting one or the other of these addresses, enabling data to be transferred to the frame memory at one rate and read out of the frame memory at another rate. For interlaced scanning, field detection circuits detect even and odd fields and generate signals which can be substituted for the most significant bits of the row addresses under control of an interlaced-mode signal, so that even-field data can be stored in one half of the frame memory and odd-field data in the other. This frame memory control system utilizes the frame memory efficiently, and can be employed with both sequential-scanning and interlaced-scanning raster display devices.

REFERENCES:
patent: 4364090 (1982-12-01), Wendland
patent: 4602275 (1986-07-01), Smith
Kobayashi, "Development of a 256K-Bit Dual-Port Memory Permitting Uninterrupted Serial Output for Frame Buffer Use," Nikkei Electronics, pp. 211-240, Aug. 12, 1985.
Kumagaya et al., "Work-Station Display Enhancement by Dual-Port Memory and Gate Array," Nikkei Electronics, pp. 225-252, Jun. 30th, 1986.

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