Frame mapping scheduler with compressed mapping table

Details Frame mapping scheduler with compressed mapping table Frame mapping scheduler with compressed mapping table

2008-04-01

2008-04-01

Duong, Frank (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

Reexamination Certificate

active

07352752

ABSTRACT:
A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a mapping table. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and a particular one of the transmission elements. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry to identify the particular transmission element. The mapping table is stored in a compressed format in memory circuitry associated with the scheduling circuitry. More specifically, the mapping table is stored as a compressed mapping table in which a particular entry identifies one of a plurality of stored values which is processed to determine a corresponding uncompressed mapping table entry.

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S.S. Panwar et al., “Golden Ratio Scheduling for Flow Control in Low Buffer Requirements,” IEEE Transactions on Communications, vol. 40, No. 4, pp. 765-772, Apr. 1992.

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