Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-04-01
2001-12-11
Boudreau, Leo (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S144000, C250S559300, C356S620000, C356S401000
Reexamination Certificate
active
06330355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to monitoring the overlay performance for chips composed of multi-exposure images and more particularly to the use of a new vernier test pattern to monitor overlay performance.
2. Description of the Related Art
As chip sizes become larger the limits of the projection system used to fabricate the chips becomes a limitation on allowable chip size. One method of overcoming this limitation is to form the chip in two separate images projected adjacent to each other on the wafer. The accuracy of the overlay or alignment of these two images is a key factor in the success of this method.
U.S. Pat. No. 4,538,105 to Ausschnitt describes an overlay test wafer for determining the overlay alignment of a second level pattern over a first level pattern.
U.S. Pat. No. 5,563,012 to Neisser describes a multi mask method of forming an image to enhance selective mask features.
U.S. Pat. No. 4,475,811 to Brunner describes an overlay test measurement system for testing lithographic instruments.
U.S. Pat. No. 5,699,282 to Allen et al. describes a method and test structures for measuring overlay accuracy in multilayer devices. The reference structure is qualified and overlay accuracy is measured using electrical measurements.
U.S. Pat. No. 5,235,626 to Flamholz et al. describes a segmented mask for an x-ray lithography system.
U.S. Pat. No. 5,695,897 to Mitome et al. describes an alignment method for a first stepper used in conjunction with a second stepper.
U.S. Pat. No. 5,668,042 to Bae describes a method for aligning micro patterns of a semiconductor device.
U.S. Pat. No. 5,766,809 to Bae describes a method for testing an overlay occurring in a semiconductor device to compensate for an error generated in the measurement of the overlay. The method uses a box-in-box pattern and an inclined measuring mark.
U.S. Pat. No. 5,701,013 to Hsia et al. describes a pattern using a box-in-box pattern for measuring overlay and critical dimensions.
SUMMARY OF THE INVENTION
Due to the limitations of the projection systems use d to fabricate large integrated circuit chips it is frequently necessary to form large chips from two separate chip images projected on the wafer. The chip images are designed so that each chip image has an overlap area where one chip image interconnects to the other chip image. It is important to have an in-process process monitor to measure the accuracy of the alignment of the two adjoining chip images. Most alignment methods are related to alignment marks on a wafer, or the like, which determine the alignment of each chip image separately.
It is a principal objective of this invention to provide a mask having a frame cell design which permits the overlay accuracy of two adjacent chip images to be monitored.
It is another principal objective of this invention to provide a mask having a frame cell design which permits the overlay accuracy of two adjacent chip images to be monitored.
It is another principal objective of this invention to provide a method of monitoring the overlay accuracy of two adjacent chip images using a mask having a frame cell designed for the monitoring purpose.
These objectives are achieved by means of alignment patterns located in the scribe line region of two chip images which can be used to align the two chip images. In one of the embodiments the alignment patterns use vernier test patterns located in the scribe line region of the two chip images which can be used to monitor the alignment accuracy directly. In one of the embodiments a box in box pattern is used. Two patterns are located in the scribe line for each of the chip images. The patterns are oriented to measure alignment in the X, or horizontal, direction and the Y, or vertical, direction. As the layer of photoresist formed on the wafer is exposed with the chip images the monitor patterns for the first and second chip images are also exposed in the layer of photoresist. The two sets of monitor patterns are arranged to measure the overlay accuracy of the two chip images. When the layer of photoresist is developed the monitor patterns transferred to the layer of photoresist can be examined to provide information about the overlay alignment in both the X and Y directions for the two chip images.
REFERENCES:
patent: 4353087 (1982-10-01), Berry et al.
patent: 4475811 (1984-10-01), Brunner
patent: 4529314 (1985-07-01), Ports
patent: 4538105 (1985-08-01), Ausschnitt
patent: 4606643 (1986-08-01), Tam
patent: 5235626 (1993-08-01), Flamholz et al.
patent: 5563012 (1996-10-01), Neisser
patent: 5668042 (1997-09-01), Bae
patent: 5692070 (1997-11-01), Kobayashi
patent: 5695897 (1997-12-01), Mitome et al.
patent: 5699282 (1997-12-01), Allen et al.
patent: 5701013 (1997-12-01), Hsia et al.
patent: 5757507 (1998-05-01), Ausschnitt et al.
patent: 5766809 (1998-06-01), Bae
patent: 6259525 (2001-07-01), David
Chen Chia-Hsiang
Hung Chih-Chien
Lee Chun-Mei
Liang De-Ming
Liu Hsiang-Chung
Ackerm Stephen B.
Boudreau Leo
Presco Larry J.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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