Frame error detection system

Details Frame error detection system Frame error detection system

1990-11-29

1992-07-21

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

3701054, 371 471, H04L 700

Patent

active

051329913

ABSTRACT:
A frame error detection system for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, which is in parallel form, detecting A1 and A2 bytes and if, in the OC-3 mode, three consecutive A1 bytes are received, followed by three A2 bytes, then framing is correct. If one of these bytes is missing, then there is an error in framing. The bytes, as they are received and processed by the system, are stored in a series of flip-flops and the output logic signal therefrom is indicative of the framing condition as to whether it is correct or errored.

REFERENCES:
patent: 3585507 (1971-06-01), Bickel
patent: 4768192 (1988-08-01), Pattavina et al.

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