Frame decoding

Multiplex communications – Wide area network – Packet switching

Patent

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Details

375116, H04J 306, H04L 708

Patent

active

047633247

ABSTRACT:
A method of frame decoding a series data flow having a frame structure containing an item of periodically occurring synchronizing information, employs a frame recognition circuit, which is synchronized to the item of synchronizing information and is coupled to a frame generator. After a predetermined number of synchronous coincidences of the item of synchronizing information and a synchronizing signal emitted from the frame generator, the frame recognition circuit and frame generator are decoupled. During synchronous coincidence, a weighting counter is periodically increased by a predetermined amount, and in the case of non-coincidence it is periodically reduced by a predetermined amount. Resynchronization takes place only when the count of the weighting counter has reached its maximum value and the frame recognition circuit is synchronized to a new item of synchronizing information.

REFERENCES:
patent: 3920900 (1975-11-01), Fineman

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