Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2000-03-07
2003-10-21
Vanderpuye, Kenneth (Department: 2732)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S395100
Reexamination Certificate
active
06636507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a frame data exchanging method and apparatus in which data is exchanged in terms of a pre-set number of frames as a unit.
2. Description of the Related Art
In communication application such as remote conferencing, large-scale distributed computing or data base, a high-speed network is required. Thus, high-speed communication by asynchronous transfer mode (ATM) has come to be used. This ATM is a technique of digitizing the information, such as speech, data or picture, splitting the information into information units of constant short lengths, switching at a high speed and transmitting the information to a counterpart side of the communication.
The current ATM switching mechanism employs roughly three systems, namely (1) an input buffer system, (2) an output buffer system and (3) a c-owned buffer system.
(1) In the input buffer system, a memory for transient storage of cells is provided in each input port. The memory is required to store the inputted cells reliably and operates at a speed higher than the information transmitting speed at the input port. The frame transfer occurs in accordance with the inputting sequence, that is in accordance with the first-in first-out (FIFO) system, so that, if the leading cell of the memory competes with other input ports as to acquisition of the output port , there is produced a head-of-line (HOL) blocking phenomenon in which succeeding cells cannot be transferred. The result is that the cells tend to be stagnant in the memory so that the cells tend to overflow from the memory to produce cell loss.
(2) The output buffer system provides a memory at each output port for transient cell storage. If the cell arrives at the input port, this cell needs to be instantly transferred to the memory of the output port. Therefore, the bus interconnecting the memories of the input and output ports needs to be operated at a speed not lower than the information transporting speed of the input port multiplied by the number of the input ports.
(3) The co-owned buffer system provides a sole buffer. The cells arriving at the totality of the input ports are immediately transferred and subsequently the cells stored in the buffer are read out by the output ports. Since the totality of the input ports and output ports communicate with the sole buffer, the bus interconnecting the buffer and the input and output ports needs to be operated at a speed not lower than the speed corresponding to a sum of the information transmission speed at the input port multiplied by the number of the input ports and the information transmission speed of the output port multiplied by the number of the output ports.
In the input buffer system (1), the bus operating speed is lower than that in the output buffer system (2) or in the co-owned buffer system (3), however, the frame loss ratio is higher than that in the output buffer system (2) or in the co-owned buffer system (3). In the output buffer system (2) or in the co-owned buffer system (3), the frame loss ratio is lower than that in the input buffer system (1), however, the bus operating speed is higher than that in the input buffer system (1).
For the above reason, it has been difficult in the conventional ATM switching mechanism to improve the cell switching speed to a value higher than a certain value as the cell loss ratio is suppressed to a lower value.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a frame switching method and apparatus in which it is possible to suppress the bus operating frequency and to suppress the cell (frame) loss ratio to a value lower than that in the ATM switching mechanism employing the conventional input buffer system.
In one aspect, the present invention provides an apparatus for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, including: input buffer means for storing frame data arriving at an input port from outside, distribution means for checking the addresses of the frame data stored in the input buffer means for associatively distributing the respective frame data to output ports, memory means connected to an downstream side of the distribution means in association with the output ports for temporarily storing the frame data distributed by the distribution means in association with the output ports, switching means for connecting the memory means to the output ports and arbitration means for controlling the switching means.
In another aspect, the present invention provides a method for switching frame data in which data is switched in terms of a pre-set number of frames as a unit, including a step of storing frame data arriving at an input port from outside in an input buffer, a step of checking the addresses of the frame data stored by the frame data storage step for associatively distributing the respective frame data to output ports, a step of temporarily storing the frame data distributed by the distribution step in association with the output ports, a step of arbitrating a switching portion between the memory and the output port in a controlled manner and a step of transferring the frame data stored in the storage step to the output port responsive to a use permission of the switching portion arbitrated by the arbitration step.
In accordance with the present invention, there may be provided a frame switching method and apparatus by means of which it is possible to suppress the operating frequency of the bus and to suppress the cell loss ratio in comparison with that in an ATM cell switching apparatus employing the conventional input buffer system.
REFERENCES:
patent: 6122251 (2000-09-01), Shinohara
patent: 6449283 (2002-09-01), Chao et al.
patent: 6563837 (2003-05-01), Krishna et al.
Hasegawa Junichi
Kunito Yoshiyuki
Miyoshi Yutaka
Maioli Jay H.
Sony Corporation
Vanderpuye Kenneth
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