Frame converter using a dual-port random access memory

Details Frame converter using a dual-port random access memory Frame converter using a dual-port random access memory

1989-07-06

1992-07-14

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 68, H04Q 1108

Patent

active

051309793

ABSTRACT:
For rearranging the time slots of an incoming frame according to a specified order and generating an outgoing frame. A time base generates timing pulses at intervals N times greater than the intervals at which the incoming and outgoing frames are generated, where N is an integer equal to or greater than 2. There is provided a dual-port random access memory capable of writing the time slots of a given incoming frame into memory cells and simultaneously reading the time slots of a rearranged version of a frame preceding the given incoming frame. A write address code is supplied to the random access memory in response to each of the timing pulses to write N successive incoming frames and a read address code is generated in accordance with a switching control signal and supplied to the random access memory in response to each of the timing pulses to read N successive outgoing frames.

REFERENCES:
patent: H586 (1989-02-01), Kun
patent: 4450557 (1984-05-01), Munter
patent: 4782479 (1988-11-01), Rozema
patent: 4941141 (1990-07-01), Hayano

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