Frame buffer system designed for windowing operations

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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Details

345 98, 345185, 345191, 395166, G06F 1200

Patent

active

055287514

ABSTRACT:
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

REFERENCES:
patent: 4648077 (1987-03-01), Pinkham et al.
patent: 4823302 (1989-04-01), Christopher
patent: 5046023 (1991-09-01), Katsura et al.
patent: 5282177 (1994-01-01), McLaury
patent: 5305078 (1994-04-01), Inoue

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