Communications: electrical – Land vehicle alarms or indicators – Internal alarm or indicator responsive to a condition of the...
Patent
1985-04-05
1988-07-05
Brigance, Gerald L.
Communications: electrical
Land vehicle alarms or indicators
Internal alarm or indicator responsive to a condition of the...
340748, 340750, 340798, 340799, G09G 116
Patent
active
047558105
ABSTRACT:
A frame buffer memory has a random access memory (RAM) for storing pixel data words, each word containing pixel data corresponding to a separate set of a plurality pixels along a horizontal raster line of a screen display. Each word is separately addressed.The RAM is organized into tiles, with each tile comprising an array of pixel data word rows and columns corresponding to a separate rectangular subset of horizontally and vertically contiguous display pixels. The RAM is addressed by sequentially applying row and column addresses. A first subset of the column address determines which pixel word row within each tile is addressed, while and a second subset of the column address determines which pixel word column within each tile is addressed. All other bits of the row and column addresses determine which tile is addressed.
Means are provided to selectively increment or decrement the first and second subsets of the column address without changing any other address bits, such that words within a selected tile row or column may be successively addressed allowing rapid reading and writing of sequences of pixel data corresponding to contiguous rows or columns of display pixels.
A first-in, first-out buffer, provided to store the sequences of data read from the RAM, also includes a barrel shifter to shift bit positions of the data words so stored to facilitate proper pixel alignment during a horizontal scrolling operation.
A logic circuit is provided to rapidly modify sequences of data read from the RAM and stored in the buffer prior to rewriting the data to the RAM thereby allowing rapid alteration of pixel attributes.
REFERENCES:
patent: 4517654 (1985-05-01), Carmean
patent: 4566002 (1986-01-01), Miura et al.
patent: 4617564 (1986-10-01), Yoshioka
patent: 4642794 (1987-02-01), LaVelle et al.
patent: 4663617 (1987-05-01), Stockwell
patent: 4694406 (1987-09-01), Shibui et al.
Bedell Daniel J.
Brigance Gerald L.
Hulse Robert S.
Tektronix Inc.
LandOfFree
Frame buffer memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frame buffer memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frame buffer memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2334938