Frame buffer cache for graphics applications

Details Frame buffer cache for graphics applications Frame buffer cache for graphics applications

1997-05-30

1999-06-01

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345517, 345518, 345513, 345521, G09G 536

Patent

active

059092254

ABSTRACT:
A frame buffer cache includes a dual-input, dual-output storage cell to multiplex frame buffer tile data and pixel data. Tile data stored in one format while pixel data is stored in a second format. The cache allows for buffering the data in the two different formats so as to provide the data in the format as needed. Pixel data is retrieved from the tile data and file data is retrieved from the pixel data. The storage cell includes a multiple-bit latch and tri-state buffers which connect each storage cell to a tile data bus and a pixel data bus. A number of bus lines and components are reduced due to the use of the tri-state buffers.

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