Frame buffer architecture for storing sequential data in alterna

Details Frame buffer architecture for storing sequential data in alterna Frame buffer architecture for storing sequential data in alterna

1989-04-03

1993-03-16

Kriess, Kevin A.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358909, 35821322, 364DIG2, 3649261, 3649263, 3649266, 3649661, 3649663, H04N 5225, G06F 300

Patent

active

051951827

ABSTRACT:
A digital frame buffer architecture is disclosed including a least two data banks, each data bank having at least a number of DRAMs equal to the number of bits in the data word to be stored. The DRAMs have a write cycle time greater than the input pixel data rate, but less than the input pixel data rate multiplied by the number of data banks provided. Succeeding input data words are alternately stored in the data banks. Sufficient time is provided to complete a write cycle as each data bank only stores every other data word.

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Toshiba Integrated Circuit Technical Data for TC514100J/Z-80, TC514100J/Z-10, Oct. 24, 1987.

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