Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
2007-07-10
2007-07-10
Ha, Dac V. (Department: 2611)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C375S362000, C375S371000, C370S509000, C370S516000, C370S520000, C713S502000, C713S503000
Reexamination Certificate
active
10463678
ABSTRACT:
A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.
REFERENCES:
patent: 3887769 (1975-06-01), Cichetti, Jr. et al.
patent: 4718074 (1988-01-01), Mannas et al.
patent: 4737722 (1988-04-01), Ramesh et al.
patent: 5428649 (1995-06-01), Cecchi
patent: 5838744 (1998-11-01), Zheng
patent: 6778623 (2004-08-01), Dietrich et al.
patent: 6836854 (2004-12-01), Ranganath et al.
patent: 2002/0025014 (2002-02-01), Jung
patent: 0 991 278 (2000-05-01), None
Skierszkan Simon J.
Wang Wenbao
(Marks & Clerk)
Ha Dac V.
Mitchell Richard J.
Zarlink Semiconductor Inc.
LandOfFree
Frame boundary discriminator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frame boundary discriminator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frame boundary discriminator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3744761