Frame based vertical panning system

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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Details

358183, H04N 3223, H04N 5262

Patent

active

052628647

ABSTRACT:
A television apparatus comprises a display for a video signal and a panning control circuit. The panning control circuit counts the horizontal lines, or half lines, and generates a vertical reset signal delayed by a variable pan delay relative to the vertical synchronizing component of the video signal. The pan delay varies in a first range for vertically panning the video signal down and varies in a second range for vertically panning the video signal up. The first and second ranges are mutually exclusive to control interline flicker of the panned video signal when successive fields have different numbers of horizontal lines. The first range is less than the number of horizontal lines in each field and the second range is greater than the number of horizontal lines in each field and less than the number of horizontal lines in each frame.

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