Frame alignment circuit

Details Frame alignment circuit Frame alignment circuit

1992-10-06

1994-07-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701052, 3701053, 370106, 375106, 375116, H04J 306

Patent

active

053274342

ABSTRACT:
A frame alignment circuit comprises a first series-to-parallel data converting means comprising a first shift register for accumulating a series data, a first latch circuit for converting the series data into a first parallel data and a first counter for dividing a clock signal into a divided clock signal; a second series-to-parallel data converting means comprising a second shift register for accumulating the first parallel data outputted from the first series-to-parallel data converting means, a second latch circuit for latching the first parallel data and outputting the first parallel data which is converted into a second parallel data and a second counter for further dividing the divided clock signal of the first counter; a frame alignment determining means for detecting a deviation of alignment based on a frame alignment pattern; and a shift controlling means for controlling at least a divided ratio of the second counter based on the deviation of alignment outputted by the frame alignment determining means.

REFERENCES:
patent: 3909541 (1975-09-01), Bobilin
patent: 4920546 (1990-04-01), Iguchi et al.
Design Considerations of Broadband Access System Components K. Murano, T. Soejima, K. Iguchi, T. Tsuda, M. Ohhata, Globecom '87 pp. 13.6.1-6. 1987.

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