Fram aligner with reduced circuit scale

Details Fram aligner with reduced circuit scale Fram aligner with reduced circuit scale

1993-07-08

1995-03-21

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

370106, H04L 700

Patent

active

054003695

ABSTRACT:
A frame aligner detects sync patterns consisting of at least two units of data having a first value followed by at least two units of data having a second value in a serial data signal. The serial signal is demultiplexed to units of parallel data, which are stored in a shift register having a capacity of two units of data. All but one bit off the stored data are scanned to detect a unit having the first value. When such a unit is detected, alignment data indicating its position in the shift register are generated. The alignment data are latched and used to extract subsequent units from the shift register. New and old alignment data are compared to detect aligned units having the first value. A sync pattern is recognized as a consecutive sequence of such aligned units followed by a consecutive sequence of units having the second value.

REFERENCES:
patent: 4835768 (1989-05-01), Habbard et al.
patent: 5081654 (1992-01-01), Stephenson et al.
patent: 5113417 (1992-05-01), McNesby
patent: 5132991 (1992-07-01), McNesby et al.
patent: 5140618 (1992-08-01), Kinoshita et al.
patent: 5313500 (1994-05-01), Rikiyama
"2.488 Gb/s SONET Multiplexer/Demultiplexer with Frame Detection Capability", by Dennis T. Kong, IEEE Journal On Selected Areas In Communications, vol. 9, No. 5, Jun. 1991, pp. 726-731.

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