Fractional PLL employing a phase-selection feedback counter

Details Fractional PLL employing a phase-selection feedback counter Fractional PLL employing a phase-selection feedback counter

1999-12-13

2003-02-25

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S005000, C703S001000, C375S376000, C327S156000

Reexamination Certificate

active

06526374

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to phase-locked loop (PLL) circuits, and, more particularly, to phase selection in a fractional-N PLL circuit.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates, or synthesizes, a periodic output signal that has a constant phase and frequency with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, “Charge-Pump Phase-Lock Loops”
IEEE Trans. Commun.,
vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference. Usually, the frequency of the output signal is higher than the frequency of the input signal.
FIG. 1
shows a block diagram of a conventional charge-pump phase-locked loop
100
. Phase detector (PD)
102
compares the phase
IN
of the input signal F
IN
to the phase
OUT
of the feedback signal F
OUT
and generates an error signal: either an UP signal U (when
IN
leads
OUT
) or a DOWN signal D (when
OUT
leads
IN
), where the width of the error signal pulse indicates the magnitude of the difference between
IN
and
OUT
.
Charge pump
104
generates an amount of charge equivalent to the error signal (either U or D) from PD
102
. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitors in loop filter
106
. For purposes of this explanation, loop filter
106
has a relatively simple design, consisting of a capacitor C
S
in parallel with the series combination of a resistor R and a relatively large capacitor C
L
. As such, loop filter
106
operates as an integrator that accumulates the net charge from charge pump
104
. Other, more-sophisticated loop filters are, of course, also possible. The resulting loop-filter voltage V
LF
is applied to voltage-controlled oscillator (VCO)
108
. A voltage-controlled oscillator is a device that generates a periodic output signal (F
OUT
in FIG.
1
), whose frequency is a function of the VCO input voltage (V
LF
in FIG.
1
). In addition to being the output signal from PLL
100
, the VCO output signal F
OUT
is used as the feedback signal for the closed-loop PLL circuit.
Optional input and feedback dividers
110
and
112
may be placed in the input and feedback paths, respectively, if the frequency of the output signal F
OUT
is to be either a fraction or a multiple of the frequency of the input signal F
IN
. If not, the input and feedback dividers
110
and
112
may both be considered to apply factors of 1 to the input and feedback signals, respectively.
When input and feedback dividers
110
and
112
are employed, the PLL output signal's frequency F
OUT
is related to the input signal's frequency F
IN
based on the counter value (R) of input divider
110
and the counter value (N) of feedback divider
112
. The relationship between the output signal frequency F
OUT
and the input signal frequency F
IN
may be as given in equation (1):
F
OUT
=
N
R
⁢
F
IN
.
(
1
)
In some PLL's of the prior art, the input and feedback dividers
110
and
112
are digital counter circuits and N and R are usually integers. However, in some applications, N may be an integer plus a fraction, such as 66⅔, and a PLL of such applications is known in the art as a fractional-N PLL. A fractional-N PLL may be implemented by having the counter value N of the feedback divider
112
switch between two different values such that the average of the two values is the desired fractional count. This scheme has the disadvantage of introducing large, instantaneous phase errors into the PD
102
whenever the value of N changes that must be corrected, usually requiring relatively complex analog circuitry.
A ring oscillator is commonly used as the VCO
108
of PLL
100
. A ring oscillator has an odd number of inverting stages, each inverting stage operating at a frequency determined by the delay through each inverting stage and the number of inverting stages in the ring oscillator. For a three-stage ring oscillator, the periodic output signals of the three inverters are 120° out of phase with each other, so the delay through one inverter is ⅓ of the period of the ring oscillator's output signal period. In PLLs of the prior art, one phase of the ring oscillator is employed to clock the counter of the divider, and the output signal of the counter is the output signal of the ring oscillator divided by the value of the counter.
SUMMARY OF THE INVENTION
The present invention relates to phase-locked loop (PLL) circuits comprising a feedback divider whose count-by-N counter is clocked with selected signal phases of the PLL output signal, the selected signal phases generated by stages of a ring oscillator of the VCO of the PLL. Since the delay added to starting the counter in the feedback path may be equivalent as each phase is selected, the phase detector of the PLL does not receive a disjoint signal from the feedback path that causes large, instantaneous phase errors
An exemplary embodiment of the invention includes a phase detector (PD), a voltage controlled oscillator (VCO), a multiplexer, and a feedback divider. The PD generates a PLL PD signal based on a difference in phase between a PLL input signal and a PLL feedback signal, wherein a circuit generates a control voltage from the PLL PD signal. The VCO generates a PLL output signal having a frequency and phase based on the control voltage, the VCO including a ring oscillator having a plurality of stages and each stage providing a corresponding signal phase of the PLL output signal. The multiplexer receives two or more signal phases of the ring oscillator and providing one signal phase based on a select signal generated from the PLL feedback signal. The feedback divider clocks a count-by-N counter (N a positive integer) with the signal phase provided by the multiplexer to generate the PLL feedback signal, wherein the counter 1) divides the signal corresponding to the selected signal phase during a cycle of N counts and 2) delays or advances the next cycle of N counts based on a difference between the current and next signal phase provided by the multiplexer.


REFERENCES:
patent: 5727038 (1998-03-01), May et al.
patent: 5889436 (1999-03-01), Yeung et al.
patent: 6075395 (2000-06-01), Saeki
patent: 6114914 (2000-09-01), Mar
patent: 6380774 (2002-04-01), Saeki
patent: 6396320 (2002-05-01), Saeki
“Charge-Pump Phase-Lock Loops,” by Floyd M. Gardner, IEEE Trans. Commun. vol. COM-28, No. 11, Nov. 1980, pp. 321-329.

Affiliated with

Also associated with

Rating

Fractional PLL employing a phase-selection feedback counter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fractional PLL employing a phase-selection feedback counter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fractional PLL employing a phase-selection feedback counter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3154329