Fractional phase-locked loop for generating high-definition...

Details Fractional phase-locked loop for generating high-definition... Fractional phase-locked loop for generating high-definition...

2006-05-16

2010-12-14

Yenke, Brian (Department: 2622)

Television

Synchronization

Sync generation

C348S555000, C348S558000, C331S00100A, C331S016000, C331S034000, C331S074000, C327S156000

Reexamination Certificate

active

07852408

ABSTRACT:
A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

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