Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2003-02-25
2004-12-28
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S048000
Reexamination Certificate
active
06836526
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to frequency synthesizing circuits and system. More particularly, this invention relates to fractional-N frequency synthesizers, where an output frequency of the synthesizer is a non-integer multiple of a reference frequency. Even more particularly, this invention relates to fractional-N frequency synthesizers where the initial output frequency, frequency increment or step size, and a difference between channel frequencies are controlled by multiple input variables.
2. Description of Related Art
A frequency synthesizer, as is known in the art and described in “Fractional-N Synthesizers—White Paper”, Staff, Conexant Systems, Inc., Newport Beach, Calif., February, 2001, is fundamentally a phased locked loop (PLL). A phase locked loop is a negative feedback oscillator that employs a phase frequency detector with a charge pump, a low pass filter, and a voltage controlled oscillator. The phase frequency detector receives a reference frequency and compares the phase of the output frequency to the phase of the input frequency and provides an error voltage indicating the difference in phase of the output frequency versus the reference frequency. The error voltage is passed through the low pass filter to eliminate any spurious transients in the error voltage. The filtered error voltage is applied to the voltage controlled oscillator. The error voltage changes the frequency of the voltage controlled oscillator until the phase and frequency of the output signal is equal to that of the reference input signal.
A phase locked loop becomes a frequency synthesizer when a frequency divider is applied between the fed back output frequency signal of the voltage controlled oscillator and the input of the phase frequency detector. The output frequency signal now becomes a multiple of the input frequency and that multiple is the modulus of the frequency divider. The frequency divider is in essence a state machine that is clocked by the output frequency signal of the voltage controlled oscillator. The output of the state machine changes state, whenever the output frequency signal has occurred the number of times of the modulus.
The frequency synthesizer becomes programmable when the modulus of the frequency divider is a digital number placed in a register of the frequency divider. The output frequency of the frequency synthesizer is an integer multiple of the reference frequency, even with a programmable modulus. Thus, the incremental frequency change for the output frequency signal is the magnitude of the frequency of the reference input.
In order to achieve an output frequency of the synthesizer that is not only an integer multiple of the reference frequency, but is a fractional multiple of the reference frequency, a fractional-N synthesizer was developed. Refer now to
FIG. 1
for a discussion of the structure and operation of a dual modulus fractional-N frequency synthesizer. As discussed above, the frequency synthesizer is essentially a phase locked loop having a phase frequency detector
10
into which the reference input signal (F
r
)
5
is applied. The phase frequency detector
10
incorporates a charge pump which provides an output voltage that is applied to the low pass filter
15
. The low pass filter
15
removes any spurious transients from the output voltage and applied the filter voltage level to the voltage controlled oscillator
20
. The filtered voltage level determines the frequency of the output signal (F
o
)
25
. The output signal (F
o
)
25
is the input to the dual modulus frequency divider
30
. The dual modulus frequency divider
30
divides the output signal (F
o
)
25
by the factor N or N+1 dependent on the mode signal
40
. The divided output signal (F
d
)
35
is applied to the phase frequency detector
10
for comparison to the reference input signal (F
r
)
5
to create the voltage level to adjust the frequency of the voltage controlled oscillator
20
.
The modulus controller
45
generates the mode signal
40
as a function of the density data input (K)
50
. The density data input (K)
50
is generally repetitively added to itself until there is an overflow of the addition. The overflow is used to cause the mode signal
40
to change the modulus of the dual modulus frequency divider
30
. The repetitively addition of the density data input (K)
50
causes the frequency of the output signal (F
o
)
25
to be determined by the equation:
F
o
=N
av
*F
r
where:
F
o
is the output signal
25
.
F
r
is the reference input signal
5
.
N
av
=N+K/
2
n
where:
N is the primary modulus of the dual modulus divider.
K is the density data input
50
.
n is the number of bits in the density data input (K)
50
.
The structure of the frequency synthesizer may be implemented in variations of the structure as described. In general the fundamental parameters are according to the following equations:
1. The step size of the increment of the frequency synthesizer is:
F
step
=F
r
*1/2
n
here:
F
step
is the step size of the increments of that the frequency synthesizer may be adjusted
F
r
is the reference input signal
5
.
n is the number of bits in the density data input (K)
50
.
2. The minimum frequency of the output signal (F
o
)
25
is:
F
o min
=N*F
r
where:
F
omin
is the minimum frequency of the output signal (F
o
)
25
.
F
r
is the reference input signal
5
.
N is the primary modulus of the dual modulus divider
30
.
3. The maximum frequency of the output signal (F
o
)
25
is:
F
o max
=(
N+
1)*
F
r
where:
F
omax
is the maximum frequency of the output signal (F
o
)
25
.
F
r
is the reference input signal
5
.
N+1 is the secondary modulus of the dual modulus divider
30
.
4. The reference input signal (F
r
)
5
is the difference between the maximum frequency and the minimum frequency of the output signal (F
o
)
25
or:
F
r
=F
o max
−F
o min
.
“A Low Phase Noise C-Band Frequency Synthesizer Using a New Fractional-N PLL with Programmable Fractionality,” Nakagawa et al., IEEE Transactions on Microwave Theory and Techniques, Volume: 44, Issue: 2, pp. 344-346, February 1996 describes a fractional-N phase locked loop that has an arbitrary denominator of the fractional division ratio as well as an arbitrary numerator and an integer part. In this case, the resulting modulus of the dividing factor N is now an averaged factor N
av
which is now found by the equation:
N
av
=N+A/M
where:
N, A, and M are programmable factors of the frequency synthesizer.
U.S. Pat. No. 6,219,397 (Park) describes a Phase-Locked-Loop-based CMOS fractional-N frequency synthesizer. The frequency synthesizer has an on-chip LC Voltage Controlled Oscillator. A higher-order discrete sigma-delta modulator is used in the fractional-N frequency synthesizer resulting in a strong attention at low frequencies for quantization noise. The synthesizer employs a noise shaping method to suppress fractional spurs using the high-order sigma-delta modulator.
U.S. Pat. No. 4,758,802 (Jackson) teaches a Fractional N synthesizer. The fractional N synthesizer includes a voltage controlled oscillator which produces an output signal that is transferred to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal from the variable divider. The synthesizer has two accumulators, the arrangement of the accumulators being such that an output signal that cancels the interpolation sidebands of the first accumulator caused by quantization errors in the first accumulator. The division ratio of the variable divider is set depending upon the output signal.
U.S. Pat. No. 5,224,132 (Goldberg) provides a programmable fractional-N frequency synthesizer The frequency synthesizer has a fractional divider using a counter to provide a fraction for the divider. The divider is used to divide the VCO output signal by N or N+1 as selected
Ackerman Stephen B.
Agency for Science Technology and Research
Knowles Billy
Saile George D.
Wambach Margaret R.
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