Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Patent
1986-11-24
1988-07-19
Gensler, Paul
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
331 17, 375120, H03L 700
Patent
active
047588020
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND TO INVENTION
The present invention relates to improvements in synthesisers of the fractional N type and in particular, to improvements for cancelling unwanted sidebands produced in such synthesisers when operating in the fractional N mode.
Frequency synthesisers usually comprise a voltage controlled oscillator (VCO) for providing an output signal and arranged in a phase lock loop. In order to adjust the frequency of the output signal of the synthesiser the output signal of the VCO is fed via a variable divider to a phase detector which provides a control signal to the VCO in the presence of a phase difference between a reference signal from a reference source and the output signal from the variable divider. The output frequency of such synthesisers can, however, only be varied as a multiple of the reference signal frequency and it is usually desirable to vary the output frequency in relatively small increments. If the reference signal frequency is reduced in order to produce sufficiently small increments the settling time of the synthesiser may be increased to an extent such that it is impractical for many applications. It has, therefore, previously been proposed to include additional circuitry in the synthesiser to enable operation in the fractional N mode and such synthesisers are generally known as fractional N synthesisers. In a fractional N synthesizer the division ratio N of the variable divider is controlled in multiples of N such that, over a number of cycles of the reference signal, the mean value of the division ratio, termed N mean, is the desired fraction of the division ratio N.
However, the operation of the synthesiser in the fractional N mode usually gives rise to a ripple signal, which in view of the phase lock loop configuration in the synthesiser, produces frequency modulation of the output signal from the voltage controlled oscillator and hence, the output signal has poor spectral purity.
In order to compensate for the ripple signal it has been proposed to include a phase modulator between the variable divider and phase detector of the phase lock loop. The phase modulator is driven with a drive signal in order to provide compensation of the ripple signal. However, accurate compensation of the ripple signal is heavily dependent on the accurate setting of the level of the drive signal to the phase modulator. Previous attempts to use feedback control to correct the level of the drive signal, and thus to provide optimum compensation of the ripple signal, have relied upon the extraction of a ripple rate signal from the control signal for the voltage controlled oscillator. However, the amplitude of the ripple signal is small compared to the amplitude of the control signal of the VCO and hence, it is difficult to control accurately the level of the drive signal for the phase modulator.
At present most fractional-N synthesisers are interpolated using either a single or a double accumulator scheme to obtain sub-reference rate output frequencies. In both cases the accumulators produce a bit stream which is applied to the variable divider. The integral of the bit stream is applied via a D/A converter to the synthesiser phase detector output. The sidebands produced by the interpolation are therefore cancelled leaving the induced frequency shift intact.
The single accumulator scheme works well so long as good tracking between the cancellation waveform and the ripple at the phase detector output is maintained. This is not easily achieved with variations in temperature, ageing and vibration. Also the initial calibration is extremely difficult due to the high sensitivities involved.
The double accumulator scheme produces a more efficient output bit stream which actually spreads out the unwanted interpolation sidebands. This results in a reduction of sideband amplitude at a rate of 20 dB per decade of interpolation over a single accumulator scheme. It achieves this by running two accumulators in a series/parallel arrangement. The two output bit streams are suitably combined to form another mo
REFERENCES:
patent: 4223389 (1980-09-01), Amada et al.
Gensler Paul
Oglo Michael F.
Pascal Robert J.
Plessey Overseas Limited
Renfro Julian C.
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