Fractional-N frequency synthesizer with cascaded sigma-delta...

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

Reexamination Certificate

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C455S076000, C455S112000, C455S216000, C375S375000, C375S373000

Reexamination Certificate

active

07024171

ABSTRACT:
Frequency synthesizer utilizing fractional-N synthesis includes a phase detector having an input receivable of a reference frequency, a loop filter arranged to receive the signal from the phase detector, a tunable oscillator arranged to receive a tuning signal generated by the loop filter and provide an output frequency and an integer divider arranged to receive the output frequency of the oscillator, divide it by a division control number (N+F) and provide the divided output frequency to the phase detector. The division control number is made up of an integer (N) and a fraction portion (F) separated into at least two different fractions. The fraction portion is generated by at least two sigma-delta converters, each processing a respective fraction with the sigma-delta converter processing a smaller fraction being driven at a lower clock rate than a sigma-delta converter processing the largest fraction. By driving the sigma-delta converter which processes a smaller fraction at a reduced clock rate, the sigma-delta converter can consume less power and be manufactured at reduced cost.

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Cris E. Hill: “All Digital Fractional-N Synthesizer for High Resolution Phase Locked Loops”, Applied Microwave & Wireless, Part 1, pp. 62-69, Nov./Dec. 1997.
Cris E. Hill: “All Digital Fractional-N Synthesizer For High Resolution Phase Locked Loops”, Applied Microwave & Wireless, Part 2 pp. 38-42, Jan./Feb. 1998.
Chipai Chou et al: “Reviewing Fractional-N Frequency Synthesis”, Microwaves & RF, Jun. 1999, pp. 53-56.
Yiping Fan: “Model, Analyze, and Simulate ΣΔ Fractional-N Frequency Synthesizers”, Part 1 of 2 parts, Microwave & RF, Dec. 2000, pp. 183-194 (no reduced clock rate, diff.structure).
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Brain Miller: “A Multiple Modular Fractional Divider”, IEEE Transactions on Instrumentation and Measurement, vol. 40, No. 3, Jun. 1991, pp. 578-583 (no reduced clock rate, diff.structure).

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