Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2002-07-10
2003-12-30
Wells, Kenneth B. (Department: 2816)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C327S156000, C327S117000, C331SDIG002, C331S016000, C331S025000
Reexamination Certificate
active
06670854
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) frequency synthesizer and, more particularly, to a fractional-N frequency synthesizer comprising a frequency synthesizer whose frequency divide ratio is variable.
2. Description of the Related Art
A conventional fractional-N frequency synthesizer using a PLL is described, for example, in Japanese patent laid-open No. 154935/1998 (counterpart of U.S. Pat. No. 5,818,303). This fractional-N frequency synthesizer described in this laid-open publication is shown in
FIG. 7
, where the conventional fractional-N frequency synthesizer is indicated by
70
and has a voltage-controlled oscillator (VCO)
76
producing an output signal of frequency fo. A part of this output signal of frequency fo is fed to a variable frequency divider
77
. The frequency divider
77
and an accumulator
78
frequency-divide the signal of frequency fo by an integer N or (N+1) varying periodically, thus producing a compared signal fp. The phase difference between a reference signal frequency fr and the compared signal fp is detected by a phase comparator
72
, which applies a voltage pulse having a pulse width corresponding to the phase difference to a charge pump circuit
73
. This charge pump circuit
73
produces an output current Icp, which is smoothed by a loop filter
75
and converted into a voltage. This voltage is used as a control voltage for the voltage-controlled oscillator
76
. Owing to this configuration, the average frequency fo of the output signal from the voltage-controlled oscillator
76
can be controlled to
fo=fr[N+
(
F/
2
n
)]
where F is a value applied to the accumulator every phase comparison period (period of fr or fp) and n is an integer determined by the n-bit register structure of the accumulator. Therefore, the average frequency fo of the output signal can be switched in a frequency width smaller than the frequency fr of the reference signal by switching F as well as N.
Under this condition, however, the frequency fo of the actual output signal constantly varies periodically, producing spurious signals off the center frequency. That is, in this conventional fractional-N frequency synthesizer
70
, the input value F is applied to and accumulated in the accumulator
78
of the n-bit structure every phase comparison period (period of fr or fp). The output is switched from 0 to 1 by an overflow signal Sov produced when the accumulator
78
overflows. The frequency divide ratio of the frequency divider
77
is switched from N to (N+1). Because of this structure, the frequency fo of the output signal is switched between fo
1
=(N+1) fr and fo
2
=Nfr periodically, i.e., every (2
n
/F) phase comparison periods. As a result, the above-described spurious signals are produced. Therefore, this conventional fractional-N frequency synthesizer
70
further includes a spurious-canceling circuit
79
to cancel out undesired spurious signals. This spurious-canceling circuit
79
produces a pulse voltage signal having a pulse width proportional to the output value of the accumulator since a timing when a reset signal is inputted to it. Another circuit is included which is driven by the pulse voltage signal and produces a spurious canceling-circuit output current Isc. This spurious-canceling current Isc and the output current Icp from the charge pump circuit
73
are added up to produce an electrical current that is smoothed by the loop filter
75
and converted into a voltage. This voltage is used as a control voltage for the voltage-controlled oscillator
76
. In this way, spurious signals produced due to periodical switching of the frequency divide ratio of the variable frequency divider
77
between N and (N+1) are canceled out.
However, spurious signals from the conventional fractional-N frequency synthesizer
70
shown in
FIG. 7
are essentially produced by the structure in which the frequency divide ratio of the variable frequency divider
77
is periodically switched between N and (N+1) by the accumulator
78
of n-bit register structure. As a result, a spectrum of periodically conspicuous intensity occurs. For example, in
FIG. 3
, as shown in a spectrum
31
, in a simulation where no spurious cancellation is performed under conditions of a reference frequency fr=1 MHz and a frequency divide ratio of 315(N)+{fraction (15/16)}, the output signal from the conventional fractional-N frequency synthesizer
70
produces a spurious signal
32
of level of −10 dB at maximum. As a result, the conventional fractional-N frequency synthesizer
70
has the problem that spurious signal cannot be reliably canceled unless the accuracy of the spurious-canceling circuit is increased. For example, where the spurious cancellation accuracy error is set to 5%, for example, using the same simulation as in
FIG. 3
, the maximum spectrum of spurious signals
42
produced by the conventional fractional-N frequency synthesizer
70
is about −36 dB, as in a spectrum
41
shown in FIG.
4
. That is, practical results are not produced. Consequently, the conventional fractional-N frequency synthesizer
70
needs an accurate spurious-canceling circuit. Hence, the circuit is made expensive.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fractional-N frequency synthesizer free of the foregoing problems and a method of operating the synthesizer.
This object is achieved by a method of operating a fractional-N frequency synthesizer in accordance with the present invention, the method starting with preparing a sigma-delta noise shaper. The integral and fractional parts of a frequency divide ratio-setting value for frequency-dividing the output signal are set. The fractional part of the frequency divide ratio-setting value is applied to the sigma-delta noise shaper every phase comparison period. The output from the sigma-noise shaper and the integral part of the frequency divide ratio-setting value are summed up. Using the resulting sum as a frequency divide ratio, the output signal is frequency-divided. The difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is produced. This difference is accumulated in the accumulator every phase comparison period. A spurious-canceling value is produced based on the accumulator's value.
In this method according to the invention, where a general third-order sigma-delta noise shaper is used as the above-described sigma-delta noise shaper, for example, a transfer function indicating the relation between the quantized output Y from the third-order sigma-delta noise shaper and input X is given by Y=X+(1−z
−1
)
3
Nq, where z
−1
indicates one sampling delay and Nq indicates quantization noise. The quantization noise Nq is almost random in nature, i.e., white noise. Accordingly, if number F indicating the fractional part of the frequency divide ratio-setting value is applied to the third-order noise shaper every phase comparison period, a random integer sequence S whose average value is equal to the fractional part F of the frequency divide ratio-setting value is produced every phase comparison period. That is, almost random integer sequence S whose average value is F is produced, the sequence S being from −3 to +4.
The output from this sigma-delta noise shaper and the integral part N of the frequency divide ratio-setting value are summed up. A sequence of almost random integers is produced. The average value of this sequence is equal to N+F. The sequence is from N−3 to N+4. This random sequence is used as a frequency divide ratio in the fractional-N frequency synthesizer. An output signal fo having a frequency that is (N+F) times as high as the reference frequency fr on average is produced. Therefore, in the sigma-delta noise shaper of the present invention, the frequency divide ratio does not vary periodically, unlike the co
Takeda Minoru
Toyama Akira
Jordan and Hamburg LLP
Nguyen Hai L.
Nippon Precision Circuits Inc.
Wells Kenneth B.
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