Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2001-05-18
2002-10-01
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S047000
Reexamination Certificate
active
06459753
ABSTRACT:
The invention relates to a device for generating a second signal having a frequency equal to a frequency of a first signal divided by a rational, non-integer number, which rational number is greater than one and, when written as a vulgar fraction, can only be written with a denominator not equal to one.
Such devices are known and are widely used in frequency synthesizers with phase locked loop circuits, also referred to as PLL frequency synthesizers hereinafter.
The frequency step size in the output signal of a PLL frequency synthesizer is equal to the input frequency. The frequency resolution is greater in proportion as the step size is smaller. If a very high frequency resolution is desired, a low input frequency should be used. In practice, a low input frequency is usually accompanied by a correspondingly small bandwidth of the PLL for preventing undesirable effects such as oscillation, etc. Small bandwidths of the PLL, however, are undesirable because they lead to a slow tuning, i.e. a long tuning period, to an inadequate suppression of phase noise of the voltage-controlled oscillator, to sensitivity to hum and noise, and to major a jitter of the clock signal. In addition, such a circuit is difficult to implement in integrated circuits.
The problems outlined above can be counteracted to a major extent by means of a device according to the invention which is characterized by means for supplying the first signal to a first of a number of delay elements connected in series for the purpose of further delaying the first signal per delay element each time by a time period equal to the period time of the first signal divided by the denominator of the vulgar fraction of the rational number, and by a combinatorial circuit which comprises a counter for counting pulses of the first signal, which counting takes place modulo the numerator of the rational number and in steps of the denominator of the rational number and results in counter scores, which combinatorial circuit comprises a decoder circuit for decoding counter scores on the basis of an algorithm determined by the rational number, said decoded counter scores appearing as an output signal each time at one output, determined by the counter score and the algorithm, of the decoder circuit, and which combinatorial circuit comprises means for combining output signals of delay elements determined by the algorithm with output signals of the decoder circuit so as to obtain the second signal.
It is achieved thereby that a divisional ratio with a rational, non-integer number can be made. The jitter of the divider circuit depends only on the intrinsic jitter of the system if the number of delay elements is equal to the denominator of the rational number.
If the number of delay elements is smaller than the denominator of the rational number, the jitter imposed on the resolution is equal to the period time of the first signal divided by the number of delay elements.
A device according to the invention has a great bandwidth and a short tuning time, little noise (low jitter, little spectral pollution), high resolution, is inexpensive, and can be readily integrated into integrated circuits.
A preferred embodiment of a device according to the invention is characterized in that the delay elements are connected as a delay locked loop circuit.
A phase locked loop circuit comprising a feedback loop is characterized in that a device as discussed above is included in the feedback loop.
A known solution for tackling the problem of a small bandwidth consists in a fast switching between two divider numbers between the output of a PLL circuit and an input thereof. This is called dither. Dividing then takes place, for example, by two larger numbers lying close together, for example 4 and 5. This is the equivalent of dividing by on average 4.5. However, the second frequency may be correct then on average, but this need not be the case instantaneously, i.e. at each and every moment. It is not possible in a simple manner in circuits of this kind to divide by two numbers having a difference smaller than one. A device according to the invention as described above does make this possible.
A phase locked loop circuit according to the invention comprising a feedback loop with dither possibility is characterized in that a device as described above is included in the feedback loop.
REFERENCES:
patent: 4295158 (1981-10-01), Nissen et al.
patent: 5218314 (1993-06-01), Efendovich et al.
patent: 5889436 (1999-03-01), Yeung et al.
patent: 3634594 (1988-04-01), None
patent: 0648016 (1995-04-01), None
Patent Abstracts of Japan, Hirahata Shigeru, “Horizontal Synchronism Reproducing Circuit,” Publication No. 62268274, Nov. 20, 1987, Application No. 61110736, May 16, 1986.
Koninklijke Philips Electronics , N.V.
Wambach Margaret R.
Waxler Aaron
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