Fractional multimodulus prescaler

Details Fractional multimodulus prescaler Fractional multimodulus prescaler

2001-03-09

2003-06-24

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C327S115000, C377S048000

Reexamination Certificate

active

06583674

ABSTRACT:

TECHNOLOGICAL FIELD
The invention concerns generally the technology of converting electric signals oscillating on a certain relatively high frequency into certain other electric signals oscillating on a certain different relatively high frequency. Especially the invention concerns the use of a fractional prescaler with multiple divisor numbers for the above-mentioned purpose.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a known circuit topology for generating oscillating signals with a certain predefined frequency. The circuit topology is known as one embodiment of the PLL or phase-locked loop concept. The component which generates the actual oscillating output signal f
out
is a VCO or voltage-controlled oscillator
101
. From the output there is a feedback connection to a prescaler
102
which converts the oscillating output signal f
out
into another oscillating signal f
div
with a lower frequency. To be exact, the frequency of the oscillating signal f
div
is a fraction of that of the oscillating output signal f
out
, i.e. the prescaler
102
divides the signal f
out
with a certain divisor or modulus. The lower frequency signal f
div
is fed into a phase detector
103
together with a very stable reference frequency f
ref
. The phase detector
103
gives a difference signal which depends on the phase difference between its input signals f
div
and f
ref
. This difference signal is filtered in a low-pass type loop filter
104
to get a control voltage signal to the VCO
101
. A mode selection signal Mode coupled to the prescaler
102
determines the divisor to be used. A typical known prescaler type is the so-called dual modulus prescaler where the mode selection signal Mode has two allowed values so that when the mode selection signal has its first value a divisor N is used and when the mode selection signal has its second value a divisor N+1 is used.
FIG. 2
illustrates a known conventional dual-modulus prescaler architecture. It consists of a first divider
201
known as the synchronous divider and a second divider
202
known as the asynchronous divider as well as of some logical gates. Each divider comprises a chain of D-flip-flops. Note that in order to preserve consistency with
FIG. 1
there appears a signal f
out
which is the input signal of the prescaler while its output is denoted as f
div
.
The synchronous divider
201
operates at full frequency, which means that all three flip-flops
203
,
204
and
205
are clocked by the input signal f
out
the frequency of which may be in the order of hundreds of MHz. Most of the time the mode selection signal Mode is low so the intermediate frequency f
int
on line
206
is determined by the loop of the first two flip-flops
203
and
204
in the synchronous divider
201
. During such times f
int
=f
out
/4, and since the effect of the asynchronous divider
202
is to divide f
int
by 32, the prescaler implements a divide-by-128 function, i.e. f
div
=f
out
/128. When the mode selection signal Mode is high and all Q-outputs from the flip-flops of the asynchronous divider
202
go high simultaneously, the control signal Ctrl on line
207
goes also high and the loop in the synchronous divider
201
is momentarily closed over three flip-flops instead of two, causing an extra delay which is equivalent to dividing by five. When the prescaler divides once by five and 31 times by four, the net effect is a division by 129, i.e. f
div
=f
out
/129.
The problem of the prescaler of
FIG. 2
is that there are three fully functional D-flip-flops which must be continuously clocked with full frequency. Taken that CMOS technology is used for hardware implementation, a total of three D-flip-flops clocked at a very high frequency presents a substantial drain of current and a serious load to the output of the VCO in the arrangement of FIG.
1
.
From the publication J. Craninckx, M. S. J. Steyaert: “A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 &mgr;m CMOS”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996, which is incorporated herein by reference, there is known the dual-modulus prescaler architecture illustrated in FIG.
3
. Here an input signal f
out
to the prescaler and its complementary differential pair {overscore (f
out
)} are fed into a divide-by-2 flip-flop
301
. The resulting differential pair of signals F
2
and {overscore (F
2
)} are once again divided by two in a second divide-by-2 flip-flop
302
which is of the known master/slave type so that it gives four output signals each of which has the frequency of one quarter that of the original frequency f
out
. The four output signals from the second divide-by-2 flip-flop
302
have mutual phase differences of &pgr;/2 radians so that they may be designated as F
4
,I; F
4
,Q; {overscore (F
4
,I)} and {overscore (F
4
,Q)}. They are coupled to the four input terminals of a phase selector block
303
which is just a controllable selection switch which couples one of its input signals at a time to its output. The output F
4
of the phase selector block
303
is coupled to a further divide-by-32 block
304
the output of which is the output signal f
div
of the prescaler.
A frequency control block
305
commands the phase selector block
303
to either simply connect one of its input signals constantly to its output or to change the selection of input signal. Most of the time the frequency control block
305
is disabled so that the prescaler implements a divide-by-128 function, i.e. f
div
=f
out
/128. When the mode selection signal Mode is high, the NAND gate
306
activates the frequency control block
305
so that on every positive edge of the output signal f
div
the control signal Ctrl instructs the phase selector block
303
to pick the next input signal. This causes in the signal F
4
a delay which is exactly enough to result in an overall effect according to which the prescaler now implements a divide-by-129 function, i.e. f
div
=f
out
/129.
The advantage of the prescaler of
FIG. 3
over that of
FIG. 2
is that there is only one flip-flop to be driven at the full clock frequency, which means a considerably lighter load to the output of the VCO in a PLL application and consumes much less power. However, the prescaler of
FIG. 3
is rather inflexible in that only two divisors can be used. Additionally it gives rise to a very harmful spike effect which means that if the transition in changing input signals in the phase selector block
303
is too fast, an unwanted transient negative voltage spike appears in the output signal of the phase selector block
303
. The authors of the reference publication propose that the spike should be eliminated by buffering a part of the control signal which controls the phase selection. To be exact, the authors suggest that a very small buffer inverter should be used to steer the control signals in order to limit their slope.
SUMMARY OF THE INVENTION
It is an object of the invention to present a prescaler architecture which enables the construction of high-speed multimodulus prescalers with low power consumption and applicability in very high clocking frequencies. An additional object of the invention is to present a prescaler architecture where the above-mentioned spike effect does not appear.
The objects of the invention are achieved by dividing an oscillating input signal into a multitude of component signals which differ in phase from each other, and using a flexibly controlled phase selector unit to compose various combinations from the component signals.
The prescaler according to the invention comprises
a component signal composer arranged to generate a number of parallel component signals that differ in phase from each other and
a controllable phase selector arranged to respond to a control signal by either selecting a constant number of unchanged ones of the parallel component signals or to repeatedly change its selection among the parallel component signals;
it is characterized in that the component signal composer is arranged to generate more than four paralle

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