Fractional-integer phase-locked loop system with a...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase

Reexamination Certificate

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C327S047000

Reexamination Certificate

active

07145367

ABSTRACT:
A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

REFERENCES:
patent: 5917352 (1999-06-01), Dunlap et al.
patent: 6288574 (2001-09-01), Neary
patent: 6952138 (2005-10-01), Hagberg et al.
Galton, I., “Fractional-N phase locked loops for frequeny synthesis,” Silicon Labs Distinguished Seminar on Mixed Signal Design, Univ. of Texas at Austin, Mar. 25, 2003.
Galton, I., “Delta-Sigma fractional-N phase-locked loops,” from Phase-Locking in High Performance Systems: From Devices to Architecture, Behzad Razavi, Wilsy-IEEE Press, Feb. 2003, p. 23-33.
Pamarti et al., “A wideband 2.4 GHz delta-sigma franctional-N PLL with a Mb/s in-loop modulation,” IEEE J. Solid-State Cir., 39(1):49-62, Jan. 2004.

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