Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Reexamination Certificate
2001-04-05
2003-04-29
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
C331S011000
Reexamination Certificate
active
06556087
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention concerns the technical field of frequency synthesizers; specifically, it concerns a frequency synthesizer that can suppress the generation of spurious components.
BACKGROUND OF THE INVENTION
Frequency synthesizers that employ a fractional frequency division type PLL circuit are known as circuits that can yield signals of the desired frequency and pull in frequencies at high speed. At present, for example, frequency synthesizers have been realized that can pull in a frequency in 300 microseconds or less even if the channel interval in the 800-MHz band is set to 25 kHz. In integer frequency division PLL, this can be called a major feature, as against a limit of only about 1.5 milliseconds at most. With regard to phase noise characteristics as well, it is about 10-20 dB better with respect to the integer type.
Such performance has made frequency synthesizers that employ fractional frequency division type PLL circuits indispensable devices in the field of wireless communication.
Symbol
101
in
FIG. 4
is an example of a conventional-technology frequency synthesizer that employs the fractional frequency division method; it has oscillator
131
, frequency divider
132
, clock generator
133
, phase comparator
134
, charge pump circuit
135
, low-pass filter
136
, compensation circuit
137
, and frequency division value setting circuit
138
.
Formed from these circuits is a negative feedback loop as described below; it is composed in such a way that signals output from the charge pump circuit are input via low-pass filter
136
into oscillator
131
, output signal OUT of a frequency corresponding to the size of the signal is output to external circuits and frequency divider
132
.
To describe the negative feedback loop of this frequency synthesizer
101
, first, output signal OUT output by oscillator
131
is input into frequency divider
132
, output signal OUT is frequency-divided by the integer frequency division value set inside frequency divider
132
, and the frequency-divided signal is input into phase comparator
134
.
Phase comparator
134
inputs the frequency-divided signal and the basic clock signal output by clock generator
133
, generates a signal that corresponds to the phase difference between the two signals, and outputs it to charge pump circuit
135
.
Charge pump circuit
135
is constituted so as to output a fixed current just for the time corresponding to the signal input from phase comparator
134
, and the signal according to this fixed current is input through low-pass filter
136
into oscillator
131
.
If the signal output by charge pump circuit
135
indicates that the frequency of the output signal of frequency divider
132
is higher than the frequency of the standard clock signal, oscillator
132
will lower the frequency of output signal OUT, and conversely, if it indicates that the frequency of the output signal of frequency divider
132
is lower than the frequency of the standard clock signal, it will raise the frequency of output signal OUT.
As a result, oscillator
131
operates so as to make the error signal output by phase comparator
134
small, so that overall a negative feedback loop is formed, and output signal OUT remains stable at the prescribed frequency.
The frequency division value set inside said frequency divider
132
is an integer frequency division value, but the size of the integer frequency division value is controlled by frequency division value setting circuit
138
, and the construction is such that the value changes periodically. As a result of the integer frequency division value changing periodically, the value to which the integer frequency division values are averaged becomes the fractional frequency division value, so a signal is obtained of a frequency that is a fractional frequency division value multiple of the standard clock signal.
For example, if (5000+⅛) is necessary as the fractional frequency division value, then the value that is the average of the integer frequency division values during the time period of 8 periods, that is, the fractional frequency division value becomes (5000+⅛) if, during eight continuous periods of the standard clock signal, the integer frequency division value is set to 5000 for just 7 periods, and the integer frequency division value is set to 5001 for the remaining 1 period.
In this case, because the integer frequency division value changes, the output voltage of charge pump
135
constantly changes, but the output of charge pump
135
is averaged by low-pass filter
136
, so when the 8-period time period is averaged, the frequency of the signal output by frequency divider
132
and the frequency of the standard clock signal will agree. As a result, the frequency of output signal OUT of oscillator
131
will be stable at a value that is fractional frequency division value (5000+⅛) times the standard clock signal.
But because the integer frequency division value changes as described above, even if output signal OUT is stable, the phase of the signal output by frequency divider
132
and the phase of the standard clock will never agree completely. Therefore every time phase comparator
134
operates, an error signal is output from phase comparator
134
(depending on the value of the fractional frequency division value, there may be a period during which no error signal is output, even if phase comparator
134
operates), and a ripple current of a size that corresponds to the phase difference is output from charge pump circuit
135
.
To describe this ripple current, FIG.
5
(
a
) is a timing chart of output signal OUT of frequency divider
132
versus the standard clock signal in the case when the fractional frequency division value is (5000+⅛). Symbol CLK in this diagram denotes the timing of the standard clock signal, and symbols T
1
-T
8
denote phases of output signal OUT of frequency divider
132
.
W
1
-W
8
express the amount of phase error between phases T
1
-T
8
of each output signal OUT of frequency divider
132
and standard clock signal CLK. These error amounts W
1
-W
8
include delay error amounts W
1
-W
4
and advance error amounts W
5
-W
8
, but the total value of the delay error amounts W
1
-W
4
and the total value of the advance error amounts W
5
-W
8
are equal. Therefore, as described above, when the phase of output signal OUT is time-period averaged for 8 periods, it is equal to the phase of standard clock signal CLK.
Symbols R
1
-R
8
in FIG.
5
(
b
) denote the output time periods of the ripple current that is output from charge pump circuit
135
when said phase error amounts W
1
-W
8
arise. Because charge pump circuit
135
is a fixed current output, the amount of electric charge of the respective ripple currents is proportional to the output time period. Denoting by +/−q the amount of electric charge of the ripple current at minimum error amounts W
4
and W
5
, the amount of electric charge of the ripple currents corresponding to error amounts W
1
-W
8
is −7 q, −5 q, −3 q, −q, q, 3 q, 5 q, 7 q.
The timing and size by which such ripple current is output has a period that corresponds to the period of the integer frequency division value, so there is the problem that spurious components arise on output signal OUT.
Thus, in order to eliminate such spurious components, measures are taken even with conventional-technology frequency synthesizer
101
; they are controlled by frequency division value setting circuit
138
, compensation circuit
137
is provided, and by the timing by which ripple currents are output from charge pump circuit
135
, a compensation current is generated that is opposite the ripple current in polarity but equal in size, and this is superimposed on output signal OUT of charge pump circuit
135
, thereby eliminating the ripple current.
Symbols C
1
-C
8
in FIG.
5
(
b
) denote the charge amount of the compensation currents corresponding to the charge amounts R
1
-R
8
of the ripple currents. The charge amount
Brady W. James
Chang Joseph
Kempler William B.
Pascal Robert
Telecky , Jr. Frederick J.
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