Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Patent
1990-03-09
1991-08-13
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
377 49, 377 39, H03K 2102, H03K 2112
Patent
active
050401971
ABSTRACT:
A frequency divider circuit is responsive to first and second digital input signals and an input clock signal for providing an output clock signal operating at a frequency equal to that of the input clock signal divided by the ratio of the first and second digital input signals. A register is initialized to a predetermined digital value for providing a first digital output signal. The first digital input signal is subtracted from the first digital output signal to form a second digital output signal for the first logic state of a digital control signal; otherwise the second digital output signal is set equal to a least significant portion of the first digital input signal for the second logic state of the digital control signal. The second digital output signal and the second digital input signal are added together for providing the next value of the first digital output signal which is stored back in the register to repeat the cycle. A most significant portion of the first digital output signal provides the digital control signal. The first logic state of the most significant bit of the first digital output signal also enables the output clock signal in sync with the input clock signal.
REFERENCES:
patent: 4318046 (1982-03-01), Sonntag
patent: 4694475 (1987-09-01), Mehrgardt
patent: 4704723 (1987-11-01), Markland
Atkins Robert D.
Codex Corp.
Heyman John S.
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