Fractional frequency divider

Details Fractional frequency divider Fractional frequency divider

2007-10-07

2009-02-17

Cox, Cassandra (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000

Reexamination Certificate

active

07492852

ABSTRACT:
A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock.

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