Fractional divisors for multiple-phase PLL systems

Details Fractional divisors for multiple-phase PLL systems Fractional divisors for multiple-phase PLL systems

2002-01-02

2003-04-01

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

06542013

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention generally relates to frequency multipliers, and in particular, to a fractional frequency multiplier.
2. Description of the Related Art
The number of different clock frequencies that are required in an electronic component continues to increase. If the required clock frequencies are integer multiples of a reference frequency, a conventional phase-locked loop (PLL) circuit may be used to synthesize the required frequencies using a reference input signal produced by a single clock source. However, circumstances exist in which the desired clock frequencies are not precisely equal to integer multiples of a reference frequency.
In certain instances, it is difficult to synthesize required frequencies for components using commonly available base frequencies, such as, for example, 33 or 133 MHz. For example, high-speed serial links on a computer platform may be configured to operate in 1.5 to 2.5 GHz range. Synthesizing such frequencies (1.5 or 2.5 GHz) from a 33 or 133 MHz clock source may not be easily implemented. Specifically, synthesizing 2.5 GHz from a 133 MHz source involves multiplying the reference frequency by a non-integer value. And synthesizing 2.5 GHz from a 33 MHz source involves using a large feedback divisor (i.e. divide-by 75) which leads to issues with instability. In such a case, because the period of the feedback clock is larger, there is more time for the frequency of the voltage controlled oscillator (VCO) to drift before obtaining a correction from the phase detector, charge pump and filter, causing undesirable jitter. Because 1.5 or 2.5 GHz cannot be easily synthesized using 33 or 133 MHz frequencies, synthesizing such frequencies may require the platform to add another clock generator at some cost or use two cascaded PLL circuits to multiply a reference frequency by a non-integer value.
One conventional technique for multiplying a reference frequency by a non-integer value involves varying the feedback divisor integer value during a predefined divide sequence in order to simulate fractional division. For example, to generate a 2.5 GHz output signal from a 133 MHz reference signal, the input reference signal needs to be multiplied by a factor of 18.75. Using the conventional technique, such fractional multiplication may be accomplished by implementing 19-19-19-18 divide sequence in the feedback loop. In this case, fractional division of 18.75 is simulated by using a divisor value of 19 during the first three divide cycles and 18 for the fourth divide cycle. Although the PLL loop filter tries to average the phase error produced during 19-19-19-18 divide sequence, some of the phase error resulting from switching between different divisor integer values gets passed through the filter and causes the VCO to generate undesirable phase jitter. However, it has been found that keeping phase jitter low is critical to the performance, especially in high frequency applications.


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