Fractional divider system and method

Details Fractional divider system and method Fractional divider system and method

2007-04-24

2007-04-24

Lam, Tuan T. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

11154095

ABSTRACT:
The present invention relates to a fractional divider system for a low-power timer with reduced timing error at wake-up. The fractional divider system includes a fractional divider circuit operable to produce an output signal. The fractional divider system also includes a high speed crystal oscillator connected to the fractional divider circuit operable to start on wake-up from the low power mode, and a high speed clock divider circuit connected to the high speed crystal oscillator circuit. The high speed crystal oscillator circuit is configured to sample the output signal and a current state of the total timing error from the fractional divider circuit. The sampled output signal is employed to trigger the high speed clock divider circuit and the sampled current state of the total timing error preloads the high speed clock divider circuit, which is operable to synchronize a first pulse of the output signal to the ideal clock timing to an accuracy within 1.5 periods of the high speed clock.

REFERENCES:
patent: 6075834 (2000-06-01), Kojima et al.
patent: 6449329 (2002-09-01), Halter
patent: 6504498 (2003-01-01), O'Brien
patent: 6725067 (2004-04-01), Marx et al.
patent: 6882698 (2005-04-01), Mukaide
patent: 2001/0027096 (2001-10-01), Lindlar
patent: 0 954 105 (1999-11-01), None

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