Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2011-05-10
2011-05-10
Cox, Cassandra (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000
Reexamination Certificate
active
07940098
ABSTRACT:
A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.
REFERENCES:
patent: 5052031 (1991-09-01), Molloy
patent: 5463337 (1995-10-01), Leonowich
patent: 5970110 (1999-10-01), Li
patent: 6005427 (1999-12-01), Morishima
patent: 6686805 (2004-02-01), Cyrusian
patent: 6784707 (2004-08-01), Kim et al.
patent: 6956407 (2005-10-01), Baig et al.
patent: 6970020 (2005-11-01), Mei et al.
patent: 7061334 (2006-06-01), Baig et al.
patent: 7084682 (2006-08-01), Jeon et al.
patent: 7109766 (2006-09-01), White et al.
patent: 7132895 (2006-11-01), Roth
patent: 7205924 (2007-04-01), Vemulapalli et al.
patent: 7312668 (2007-12-01), Li et al.
patent: 7557623 (2009-07-01), Moehlmann et al.
patent: 7715515 (2010-05-01), Olsson et al.
patent: 2002/0008557 (2002-01-01), Abdel-Maguid et al.
patent: 2002/0033737 (2002-03-01), Staszewski et al.
patent: 2006/0133559 (2006-06-01), Glass
patent: 2006/0164176 (2006-07-01), Li et al.
Dorin Emil Calbaza, et al., “Direct Digital Frequency Synthesis of Low-Jitter Clocks,” IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp. 570-572.
Y.-C. Bae and G.-Y. Wei, “A Mixed PLL/DLL Architecture for Low Jitter Clock Generation”, IEEE International Symposium on Circuits and Systems, May 2004, pp. 788-791.
F. Zarkeshvari, T. Kwasniewski, “Analog DLL-Based Period Synthesis Circuit”, Proc. International Conference on Communication, Circuit and Systems, vol. 2, pp. 1095-1098, Hong Kong, May 2005.
F. Zarkeshvari, P. Noel, T. A. Kawasniewski, “On ΔΣ Fractional-N Frequency Synthesizers”, International Symposium on Signals, Circuits and Systems, ISSCS 2005, Jul. 14-15, Iasi, Romania, pp. 509-512.
F. Zarkeshvari, P. Noel, T. A. Kawasniewski, “PLL-Based Fractional-N Frequency Synthesizers”, Proceedings of the 9th International Database Engineering & Application Symposium, 2005, pp. 1-7.
P. Noel, F. Zarkeshvari, T. A. Kawasniewski, “Recent Advances in High-Speed Serial I/O Trends, Standards and Techniques”, Canadian Conference on Electrical and Computer Engineering, IEEE CCECE05, Saskatoon, May 2005, pp. 1292-1295.
Kwasniewski Tad
Zarkeshvari Farhad
Altera Corporation
Cahill Steven J.
Cox Cassandra
LandOfFree
Fractional delay-locked loops does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fractional delay-locked loops, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fractional delay-locked loops will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2689579