Fractional clock divider using digital techniques

Details Fractional clock divider using digital techniques Fractional clock divider using digital techniques

2005-03-01

2005-03-01

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000, C377S048000

Reexamination Certificate

active

06861881

ABSTRACT:
A fractional clock divider system and method is provided. The clock divider is configured to provide an output clock signal in response to an input clock signal. The frequency of the output clock signal may be an integral or fractional division of the input clock signal. The output frequency is equal to: (ref_freq*2)/mul, where ref_freq is the frequency of the input clock signal, and mul is a selected integer that is greater than one. The positive and negative edges of the input clock are counted to provide a positive count and a negative count respectively. A table is configured to store preselected reference values. A logic circuit is configured to control the output clock signal such that an appropriate clock transition occurs in the output clock signal when the positive and negative count reach the corresponding preselected reference values.

REFERENCES:
patent: 5249214 (1993-09-01), Ulmer et al.
patent: 5384816 (1995-01-01), Prysby et al.
patent: 6489817 (2002-12-01), Wong et al.

Affiliated with

Also associated with

Rating

Fractional clock divider using digital techniques does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fractional clock divider using digital techniques, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fractional clock divider using digital techniques will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3383015