Fraction bus for use in a numeric data processor

Details Fraction bus for use in a numeric data processor Fraction bus for use in a numeric data processor

1982-01-22

1984-11-20

Smith, Jerry

Boots, shoes, and leggings

364736, 364761, G06F 744

Patent

active

044842597

ABSTRACT:
A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words of BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.

REFERENCES:
patent: 3434114 (1969-03-01), Arulpragasam et al.
patent: 3594565 (1971-07-01), Ragen
patent: 3603934 (1971-09-01), Heath, Jr.
patent: 3641331 (1972-02-01), Kreidermacher et al.
patent: 3900723 (1975-08-01), Bethany et al.
patent: 3926367 (1975-12-01), Bond et al.
T. Chen, "Efficient Arithmetic Apparatus and Method", IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, pp. 328-330.

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